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About the research migration
  • Proposer Name: Mr Sabarish Mohan Js
  • Title of the research migration: Design and Simulation of Sayem Gate Using CMOS Technology in VLSI Systems
  • Source of the Project: 1. Journal : Journal of resource management and technology. Title : Boolean Low Power Logic Circuits with Reversible Gate by Rajkumar Jarpula(Vol2, Issue 2, 2020) 2. Journal : Institute of Electrical and Electronics Engineers Title : Low Power Boolean Logic Circuits using Reversible Logic Gates by Prashant. R.Yelekar (M.Tech) ,Prof. Sujata S. Chiwande Lecturer YCCE, Nagpur(Page 7)
  • University: Anna University