Research Migration in Progress
Work is in progress for the following submissions under the Research Migration Project
| No | Research Migration Project | Contributor Name | Institute | Year |
|---|---|---|---|---|
| 282 | Design and Performance Analysis of a Common Source MOSFET Amplifier Using eSim | Vadla Bhavya | Bvrit Hyderabad College Of Engineering For Women | 2026 |
| 281 | Design and Simulation of a Low-Voltage Bulk-Driven Second-Generation Current Conveyor (CCII) | Krishna Harikumar | Muthoot Institute Of Technology And Science | 2026 |
| 280 | CMOS Implementation of a Current-Mode Winner-Take-All (WTA) Network with O(N) Complexity | Muhammed Muhad | Muthoot Institute Of Technology And Science | 2026 |
| 279 | binary (0000-1111) to (0-F) 7-Segment Decoder | Om Laxmikant Kolhapure | Jawahar Education Societys Annasaheb Chudaman Patil College Of Engineering, Kharghar, Navi Mumbai | 2026 |
| 278 | Design and Simulation of a Simple DC Voltage Stabilization Circuit using Zener Diode in eSim | Praket Singhal | Rajjv Gandhi Institute Of Petroleum Technology | 2026 |
| 277 | Design and Performance Analysis of a Fair Round-Robin Arbiter for Resource Scheduling using eSim | Jeeva S | Karpagam College Of Engineering | 2026 |
| 276 | Design and Simulation of a CMOS Differential Amplifier with NMOS Input Pair and PMOS Active Load | Riyajuddin Md | Rajiv Gandhi University Of Knowledge And Technologies | 2026 |
| 275 | Design and Simulation of an Asynchronous FIFO Using Gray Code Pointer Synchronization | Sathya S | Karpagam College Of Engineering | 2026 |
| 274 | Implementation of Power-Efficient CMOS D Flip-Flop Using Leakage Reduction Techniques in eSim | Haridharan D | Chennai Institute Of Technology | 2026 |
| 273 | Folded MOS CML D-latch | Pandiyarajan.s | Chennai Institute Of Technology | 2026 |
| 272 | Design and Simulation of Ramp Type Analog-to-Digital Converter Using Comparator and Counter in eSim. | Purven Khadke | Marathwada Mitramandal College Of Engineering | 2026 |
| 271 | Design and Transient Analysis of a 4×4 Hybrid Booth–Dadda Multiplier Using eSim | S. Padhmanethrri | Sri Sivasubramaniya Nadar College Of Engineering | 2026 |
| 270 | Low-Power CMOS and BiCMOS Circuits for analog Convolutional Decoders | Aarunam Arune | Amrita Vishwa Vidhyapeetham Coimbatore | 2026 |
| 269 | Efficient Implementation of 3-input XOR Gate using 4*1 MUX using eSim | Riyajuddin Mohammad | Rajiv Gandhi University Of Knowledge And Technologies, Nuzvid | 2026 |
| 268 | Design and Simulation of a Full-Wave Rectifier with Automatic Load Selection Using eSim. | Randhir Jagruti Rakesh | S.v.k.m. Institute Of Technology,dhule | 2026 |
| 267 | Design a Full Bridge Inverter Circuit Using IC555 | Sandesh Rajendra Narake | Shri Guru Gobind Singhji Institute Of Engineering And Technology, Nanded | 2026 |
| 266 | Migration of a Subthreshold Izhikevich Silicon Neuron to eSim/Sky130 | Peerzada Arsalan Masoodi | Shri Mata Vaishno Devi University | 2026 |
| 265 | Design and Simulation of a Current-Controlled Negative Impedance Converter Using Op-Amp | Richa Datta | Vit Bhopal | 2026 |
| 264 | 8-bit Ripple Carry Adder (RCA) | Nishtha Singh | Manipal University Jaipur | 2026 |
| 263 | Design and simulation of LDO voltage regulator. | Mohd Ubaid | Zakir Hussain College Of F Engineering And Technology | 2026 |
| 262 | Design and implementation of a 4-to-2 binary encoder using basic logic gates | Pooja S | Rajalakshmi Institute Of Technology | 2026 |
| 261 | Simple Chaotic Systems and Circuits | Agastya Bharadwaj | Rajiv Gandhi Institute Of Petroleum Technology | 2026 |
| 260 | 12 Bit Binary Counter | Yogeswaran I | Meenakshi Sundararajan Engineering College | 2026 |
| 259 | Design and Implementation of a 4-Bit Magnitude Comparator for Digital Data Comparison.. | Kishori S | Rajalakshmi Intitute Of Technology | 2026 |
| 258 | MOS Current Source with Source Degeneration | Varsha Priya Gurram | Indian Institute Of Information Technology Sricity | 2026 |
| 257 | Design and Simulation of a 2-to-4 Line Binary Decoder using Basic Logic Gates | Lingeshram S R | Rajalakshmi Institute Of Technology | 2026 |
| 256 | Design and Analysis of an Analog Tamper / Security Detection Circuit Using eSim | Palaniraj M | Chennai Institiute Of Technology | 2026 |
| 255 | Design and Simulation of a CMOS Cascode Low Noise Amplifier | Krisanth M | Chennai Institute Of Technology | 2026 |
| 254 | Improved Sense Amplifier Based Flip FLop | Prajeen | Meenakshi Sundararajan Engineering College | 2026 |
| 253 | : Design and Simulation of a Low-Power CMOS Operational Amplifier Using eSim | S V Gokul | Chennai Institute Of Technology | 2026 |
| 252 | Design and Simulation of Voltage-Controlled Ring Oscillator with Digital Frequency Measurement in eSim | A Athul Krishna | Chennai Institute Of Technology | 2026 |
| 251 | CMOS Logic Gate for Voltage Scaling Analysis | Ravindhar M | Chennai Institute Of Technology | 2026 |
| 250 | DESIGN AND SIMULATION OF A LOW DROPOUT (LDO) VOLTAGE REGULATOR USING eSim | Lohit Bibar | Dr. B. C. Roy Engineering College, Durgapur | 2026 |
| 249 | Op-Amp Based Voltage Comparator Circuit using eSim. | Numan Rashid | School Of Electronics Engineering, Vit Bhopal | 2026 |
| 248 | Circuit-Level Design and Simulation of a Wideband Voltage Buffer Amplifier for Precision AC Signal Applications Using eSim | Siddharth Dubey | Vit Bhopal University | 2026 |
| 247 | Design and Simulation of an OTA-Based Tow-Thomas Tunable Low-Pass Filter Using eSim | Raghoothama Rao K S | Rns Institute Of Technology | 2026 |
| 246 | Design and Simulation of a Transmission-Gate Based Edge-Triggered CMOS D Flip-Flop Using eSim | Supraja Lakshmi Bharani Babu | Chennai Institute Of Technology | 2026 |
| 245 | Programmable Clock Divider with Variable Division Factor | M D Yogavelan | Chennai Institute Of Technology | 2026 |
| 244 | Optimized Low-Power 4-Bit Johnson Counter Using Negative Edge Triggered Master–Slave D Flip-Flops | Praveen R | Chennai Institute Of Technology | 2026 |
| 243 | Design and Simulation of a Glitch-Free Clock-Gating Cell for Low-Power VLSI Systems Using eSim | S Padhmanethrri | Ssn College Of Engineering | 2026 |
| 242 | 8-bit 4x4 Crossbar Switch with Round Robin Arbitration for NoC | Chaitanya Sabnis | Pvg'S College Of Engineering, Technology And Management | 2026 |
| 241 | 555 Timer Based PWM Controlled DC Motor with Back-EMF Speed Monitoring | Bhanu Pratap Singh Rathore | Poornima College Of Engineering | 2026 |
| 240 | A three-phase 12-pulse controlled rectifier | Digambar Wagholikar | Shri Guru Gobind Singhji Institute Of Engineering And Technology (sggsie&t), Vishnupuri, Nanded | 2026 |
| 239 | SOFT-ERROR RESILIENT COMBINATIONAL LOGIC USING GATE-LEVEL REDUNDANCY | Kukshi Jhawar | Vellore Institute Of Technology | 2026 |
| 238 | Design and Implementation of a Synchronous MAC Unit | Ayushmaan Ghorui | National Institute Of Technology, Tiruchirappalli | 2026 |
| 237 | Noise-Aware Design of CMOS Common-Source Amplifier | Ayush Shukla | Vellore Institute Of Technology | 2026 |
| 236 | Design and Simulation of an OTA-Based Low Dropout Voltage Regulator In eSim | Kartheesan K | Vit Chennai | 2026 |
| 235 | Design and simulation optimization of phase-locked loop structure for phase-shifting power supply | Allan Fernandes | Fr Conceicao Rodrigues College Of Engineering | 2026 |
| 234 | Power Efficient Radix-4 Booth Multiplier with Pre-encoding using eSim | Pranav K Nair | Government Engineering College Thrissur | 2026 |
| 233 | Simulation of Single-Phase AC Voltage Controller Using TRIAC | Chinnahyderabad Sandhya | B V Raju Institute Of Technology, Narsapur | 2026 |
| 232 | Design and Simulation of a Programmable Modulo-N Synchronous Down-Counter with Load Enable | Samruddhi Mali | Dr. D.y. Patil Institute Of Technology, Pune | 2026 |
| 231 | Project Title: FSM-Based Priority Elevator Control System with Emergency Override | Rohan Karadkar | Dr. D. Y. Patil Institute Of Technology Pimpri, Pune | 2026 |
| 230 | Design and Simulation of a Low Dropout Voltage Regulator using eSim | Bandanadam Pranathi | B V Raju Institute Of Technology | 2026 |
| 229 | Design and Optimisation of a Two Stage CMOS Operational Amplifier for High Phase Margin and Low Power Using eSim | Sarthak Mani | Vit Bhopal University | 2026 |
| 228 | Broken Rotor Bar Fault Detection in AC Induction Motor Using Motor Current Signature Analysis (MCSA) | Devvela Vennela | B V Raju Institute Of Technology | 2026 |
| 227 | DESIGN AND ANALYSIS OF CMOS TRANSIMPEDANCE AMPLIFIER WITH VOLTAGE AMPLIFICATION FOR HIGHER BANDWIDTH AND LOW NOISE LEVEL | Madhumitha G | Madras Institute Of Technology | 2026 |
| 226 | Analysis And Simulation of Zero Crossing Detector using Op-Amp Comparator | Bane Rajesh Hanumant | Shri Guru Gobind Singhji Institute Of Engineering And Technology Vishnupuri ,nanded-431606 | 2026 |
| 225 | Design and Implementation of an Area-Efficient 16-Bit Carry Select Adder Using Binary Excess-1 Converter | Rajyalakshmi Vanjala | Rajiv Gandhi University Of Knowledge Technologies, Nuzvid | 2026 |
| 224 | Design and Simulation of a Current Sense Amplifier using eSim | Bharanidharan R | Karpagam College Of Engineering | 2026 |
| 223 | ECG FRONT END AMPLIFIER | Sharnitha S | Sns College Of Technology | 2026 |
| 222 | Design and Simulation of a Pass-Transistor-Enabled Split Input Voltage Level Shifter for Ultra-Low-Power Applications | Shrutipriya Hosmani | Ramaiah Institute Of Technology | 2026 |
| 221 | Design and Simulation of a Memristor-Based AND/OR Logic Gate (MRL) using Behavioral Modeling | Lena Mariya Thomson | Christ College Of Engineering,irinjalakuda | 2026 |
| 220 | Design and Simulation of a CMOS Differential Amplifier with Active Load Using eSim | Sanket Kar | Dr.b.c.roy Engineering College, Durgapur | 2026 |
| 219 | Design and Simulation of Smart Helmet Accident Detection Circuit Using eSim | Praveen Kumar Patel | Vit Bhopal University | 2026 |
| 218 | FSM-Based Hardware Trojan with Logic Locking | Harikrishnan M | Government College Of Technology , Coimbatore | 2026 |
| 217 | Two-Stage Continuous-Time Linear Equalizer (CTLE) | Jayanth Krish Ramakrishnan | Manipal Institute Of Technology | 2026 |
| 216 | Design and Simulation of a Dual-Mode MOSFET Current Reference with Subthreshold and Strong Inversion Operation Using eSim | Silambarasan C V | Government College Of Technology,coimbatore | 2026 |
| 215 | A 2.4 GHz Reconfigurable Cascode/Folded-Cascode Inductive Source Degenerated LNA With Enhanced OP1dB and OIP3 Over Gain Reduction | Gopavarapu Sai Babu | Rajiv Gandhi University Of Knowledge And Technologies, Nuzvid | 2026 |
| 214 | Single-Supply, Low-Input Voltage, Full-Wave Rectifier Circuit | Manoj Krishnan R M | Government College Of Technology,coimbatore | 2026 |
| 213 | Ultra-Low Power Programmable Bandwidth CapacitivelyCoupled Chopper Instrumentation Amplifier Using 0.2 V Supply for Biomedical Applications | Sridharan S | Sri Eshwar College Of Engineering | 2026 |
| 212 | Adaptive Noise-Cancelling Smart Earbuds using Op-Amp & Adaptive Filtering for Dynamic Environments | Narayan Gupta | Dr. Ambedkar Institute Of Technology For Divyangjan | 2026 |
| 211 | Design and Simulation of a Low-Power UART Transmitter–Receiver System Using eSim | Yasaswini Kunapareddy | Bvrit Hyderabad College Of Engineering For Women | 2026 |
| 210 | Resistor-less Sub-1V CMOS Voltage Reference using Self-Cascode Composite Transistors | Debraj Saha | Jadavpur University | 2026 |
| 209 | Design and Simulation of a Smart Electronic Donation Box with Coin Detection, Counting and Indication using eSim | Shiva Singh | Vit Bhopal University | 2026 |
| 208 | Development of a Low-Noise High-Voltage Amplifier for Precision Piezoelectric Actuators | Srinivas Yelamarthi | Rajiv Gandhi University Of Knowledge Technologies - Srikakulam | 2026 |
| 207 | Ultra-Low Power Subthreshold Quasi Floating Gate CMOS Logic Family for Energy Harvesting Applications | Y Alekhya | Bvrit Hyderabad College Of Engineering For Women | 2026 |
| 206 | 2nd Order Butterworth Low Pass Filter | Jovin P John | Albertian Institute Of Science And Technology | 2025 |
| 205 | Happy Birthday Design Problem | Naresh Lankalapalli | Rajiv Gandhi University Of Knowledge Technology Srikakulam | 2025 |
| 204 | Design and Simulation of FM Modulation and Demodulation Using BC547 BJT in eSim for Analog Communication Analysis | Sanchi Ramteke | Shri Guru Gobind Singhji Institute Of Engineering And Technology (sggsiet) | 2025 |
| 203 | Design of Chebyshev Analog Bandpass Filter for Human Sound Frequency | Sudipta Dhar | Indian Institute Of Engineering Science And Technology, Shibpur (iiest) | 2025 |
| 202 | Design and Simulation of a Multi-Resolution Digital PWM Core with Programmable Duty-Cycle and Dead-Time Using Flip-Flops and Logic Gates | Kavin | Sri Eshwar College Of Engineering | 2025 |
| 201 | Implementation of 555 Timer Astable Multivibrator with Op-Amp & 2N2222 | Kavin Kumar G S | Sri Eshwar College Of Engineering | 2025 |
| 200 | Two digit ( 00 - 99 ) BCD to 7-segment Decoder | Logeshwaran S | Sri Eshwar College Of Engineering | 2025 |
| 199 | Simulation and Performance Analysis of the Traditional Phase and Frequency Detector | Abhinandan Paul | National Institute Of Technology, Silchar | 2025 |
| 198 | CMOS Counter/Dividers - High Voltage CD4017B Decade Counter and CD4022 Octal Counter | Shaivee Sharma | Kirori Mal College | 2025 |
| 197 | Enhanced Double Tuned RF Resonant Amplifier | Prakatheesh S | Sri Eshwar College Of Engineering | 2025 |
| 196 | TLC272 Peak Detector Circuit Design | Arjunan J | Sri Eshwar Engineering College | 2025 |
| 195 | Amplitude Stability in Pierce Crystal Oscillator | Rakesh R | Sri Eshwar College Of Enginneering. | 2025 |
| 194 | Design and Implementation of a Dual Edge Triggered Flip-Flop | Nabajyoti Gogoi | National Institute Of Technology, Silchar | 2025 |
| 193 | : A Square Root Carry select adder using esim | Harikrishnan R | Care College Of Engineering,trichy | 2025 |
| 192 | Two-Stage CMOS Op-Amp with Miller Compensation | Kishor S A | Chennai Institute Of Technology | 2025 |
| 191 | Design of Wallace Tree Multiplier using Approximate Full Adder and Kogge Stone Adder by using eSim. | Dharun Anandhan V | Care College Of Engineering,thayanur,trichy | 2025 |
| 190 | Design All N-Transistor Logic based Carry lookahead adder using eSim. | Jarul Shaj J | Care College Of Engineering,thayanur,trichy | 2025 |
| 189 | Single-Phase Bridgeless Buck Rectifier | B.sarnitha | Sri Eshwar College Of Enginnering | 2025 |
| 188 | Fredkin Gate Simulation | Tanaya Bane | Fr. Conceciao Rodrigues College Of Engineering | 2025 |
| 187 | Integrated Gate Drivers Based on High-Voltage Energy Storing for GaN Transistors | Shloka Shetty | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 186 | D Flip Flop With Tristate Inverter | Anushha K Shahe | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 185 | InGaAs/InP Single Photon Avalanche Diodes with Negative Feedback | Swaraj Yogesh Shelar | Fr Conceicao Rodrigues College Of Engineering | 2025 |
| 184 | Development of High Power LED Driver | Jude Fernandes | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 183 | A Divide-by-2 Frequency Divider Design | Sharanya Kotian | Fr Conceicao Rodrigues College Of Engineering | 2025 |
| 182 | A Novel Dual-Mode Dual Type Hysteresis Schmitt Trigger and its Applications using Single Differential Voltage Current Conveyor Transconductance Amplifier | Anuj Naik | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 181 | Practice And Application of Multisim in digital Electronic experiment teaching | Suvarna Suratsingh Rajput | Fr.conceicao Rodrigues College Of Engineering | 2025 |
| 180 | A Design and Analysis of Op Amp Twin-T Band Reject Notch Filter | Latika Gupta | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 179 | Design on pseudo resistors in biomedical cmos circuits | Joel Devassy | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 178 | Differential Amplifier used in the PCB | Siddhi Pawar | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 177 | Considerations on External Heat Transfer in Saturated Bipolar Junction Transistors | Daksh Marathe | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 176 | Assessing SiCr resistor drift for automotive analog ICs | Siddhesh Kulkarni | Fr Conceicao Rodrigues College Of Engineering, Bandra | 2025 |
| 175 | A Low-Power, Low-Cost Infra-Red Emitter in CMOS Technology | Joshua Daniel Mendes | Fr Conceicao Rodrigues College Of Engineering | 2025 |
| 174 | DESIGN AND IMPLEMENTATION OF AUTOMATIC TEMPERATURE MONITOR AND REGULATORY SYSTEM | Jostal Fernandes | Fr Conceicao Rodrigues College Of Engineering | 2025 |
| 173 | Design and Implementation of Low Power 3-bit Encoder Using Memristor on LTSpice | Tanmay Sanjay Sarode | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 172 | A PROPOSED CIRCUIT OF DARLINGTON PAIR BASED ON TRIPLE JFET CONFIGURATION | Nishad Athalye | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 171 | Error Analysis of Approximate Calculation of Voltage Divider Biased Common-Emitter Amplifier | Thea Dcruz | Fr Conceicao Rodrigues College Of Engineering | 2025 |
| 170 | Design, construction and calibration of automatic street light controller using Light Dependent Resistor (LDR) | Atharva Chaudhari | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 169 | The proposed on-chip BJT spread compensation topology utilizing a deep-saturated BJT Qd. | Devona Lewis | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 168 | Adaptive Resolution ADC Array for an Implantable Neural Sensor | Hanan Fernandes | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 167 | Analysis and Design of BJT Differential Amplifier | Aahana Alexus Peter | Fr. Conceicao Rodrigues College Of Engineering | 2025 |
| 166 | low noise amplifier | Kommineni Manvitha Chowdary | Srm Institute Of Science And Technology | 2025 |
| 165 | Wein Bridge Oscillator | Kartik Sharma | Model Institute Of Engineering And Technology | 2025 |
| 164 | 8-BIt Arithmetic Logic Unit | P Hari Ram Nikil | Srm Institute Of Science And Technology | 2025 |
| 163 | Royer Oscillator | Tharun D | Srm Institute Of Science And Technology | 2025 |
| 162 | llc convertor | Sujera | St.xaviers Catholic College Of Engineering | 2025 |
| 161 | Four Digital combination key using a 74HCT688 comparator IC | Bhavya Bj | Sastra Deemed University | 2025 |
| 160 | DESIGN OF POWER EFFICIENT PRIORITY ENCODER | Gobega S | Sastra Deemed University Thanjavur | 2025 |
| 159 | Performance-Driven Design of Two-Stage CMOS Op-Amp Using Bio-Inspired Dung Beetle Optimization Algorithm | Monish Kabiri | Zakir Husain College Of Engineering & Technology | 2025 |
| 158 | Power Line Communication (PLC) Module: Data Transfer Across Utility Wires (Transmitter and Receiver Simulation) | Shashwat Pandey | B.tech Electronics And Communication | 2025 |
| 157 | Three Stage DC-DC Boost Converter | Amirtha Varshiniy M A | St Xavier'S Catholic College Of Engineering | 2025 |
| 156 | Automatic Water Pump Control Circuit based on Sequential Logic (SR Latch) | M.mathi Malar | Sastra Deemed University | 2025 |
| 155 | Latch Comparator with adjustable Hysteresis using eSim | Jitheshkrishna R | Chennai Institute Of Technology | 2025 |
| 154 | Universal shift register with low power consumption | Virutchika K | Sastra Deemed University | 2025 |
| 153 | Simulation of Phase Shift Oscillator | N Misazhini | Sastra Deemed University | 2025 |
| 152 | Design and Analysis of a Low Dropout Voltage Regulator in 130nm technology node | Md Ghalib Hussain | Zakir Husain College Of Engineering And Technology | 2025 |
| 151 | To design and construct Monostable multivibrator using op amp | M.niveditha | Karunya Institue Of Technology And Sciences | 2025 |
| 150 | Timer Circuit Using OTRA and its Application as Astable and MonostableMultivibrator using esim | Neeraj G | Chennai Institute Of Technology | 2025 |
| 149 | Common emitter amplifier with voltage divider bias | Hari Haran V | Vel Tech Multi Tech Dr.rangarajan Dr.sakunthala Engineering College(autonomous) | 2025 |
| 148 | DESIGN OF A LOW-POWER SHIFT REGISTER WITH FINE-GRAINED CLOCK GATING IN ESIM | Gautam Suresh | Chennai Institute Of Technology | 2025 |
| 147 | Design and Simulation of a Power-Efficient 16:1 Multiplexer Using TGL with Power Gating | Deepak Prabakaran | Chennai Institute Of Technology | 2025 |
| 146 | TWO-STAGE BJT AMPLIFIER. | Deepeshkumar A | Vel Tech Multi Tech Dr.rangarajan Dr.sakunthala Engineering College(autonomous) | 2025 |
| 145 | Analysis and Design of a Double Tuned Clapp Oscillator for Multi-Band Multi-Standard Radio | Panshul Rastogi | Hindustan College Of Science And Technology (hcst) Mathura | 2025 |
| 144 | Passive-Linearized CMOS Class-AB Power Amplifier for BLE 4.0 | Prahas | Hindustan College Of Science And Technology | 2025 |
| 143 | IMPLEMENTATION OF SIMPLIFIED MOS-ONLY LOW-VOLTAGE BANDGAP REFERENCE IN ESIM | Merlin Jennifer S | Chennai Institute Of Technology | 2025 |
| 142 | Design, Simulation, and Performance Analysis of an 8-bit Successive Approximation Register (SAR) Analog-to-Digital Converter | Tatikonda Ramakrishna | Chennai Institute Of Technology | 2025 |
| 141 | To design a class-C power amplifier (low power) that could be potentially used for biomedical applications such as medical implants and smart wearable | Ayutansh Sharma | Hindustan College Of Science And Technology | 2025 |
| 140 | IMPLEMENTATION OF 4-BIT BINARY COMPARATOR USING OPTIMIZED 12T LOGIC IN ESIM | Edna Joy J | Chennai Institute Of Technology | 2025 |
| 139 | Design and analysis of single stage amplifier | Harini M V | Sri Eshwar College Of Engineering | 2025 |
| 138 | Optimized 4-Bit Binary-to-Gray Code Converter for VLSI Applications Using MUX-XOR Design | Priyadharsan D | Chennai Insitute Of Technology | 2025 |
| 137 | Multiplexer-Based Implementation of Digital Adder Circuits using eSim | Senthil Kumar Mahalingam | Chennai Institute Of Technology | 2025 |
| 136 | Design and Simulation of a First-Order Sigma-Delta (ΔΣ) ADC with Digital Decimation in eSim | Gouri Saxena | Vit Bhopal | 2025 |
| 135 | Design of an Analog Front-End for ECG Signal Conditioning | Krisanth M | Chennai Institute Of Technology | 2025 |
| 134 | IMPLEMENTATION OF MODIFIED CARRY SELECT ADDER USING BINARY EXCESS-1 CONVERTER IN ESIM | Yogavelan M D | Chennai Institute Of Technology | 2025 |
| 133 | IMPLEMENTATION OF TWO-STAGE CASCODED OTA BASED LOW-DROPOUT (LDO) VOLTAGE REGULATOR IN ESIM | Praveen R | Chennai Institute Of Technology | 2025 |
| 132 | IMPLEMENTATION OF 4-BIT GRAY-CODE COUNTER USING BINARY COUNTER AND XOR-ONLY BINARY→GRAY CONVERTER IN ESIM | Priyadharsan Dhanasekar | Chennai Insitute Of Technology | 2025 |
| 131 | 3-Bit Majority Function & LZS | Rupesh Nawin S | Sri Eshwar College Of Engineering | 2025 |
| 130 | Design and Analysis of Temperature Compensated Log Amplifier Using Op-Amp and Diode | Karthiban S T | Sri Eshwar College Of Engineering | 2025 |
| 129 | RISC-V Mini CPU Design and Simulation | Malothu Anil Kumar | Cmr College Of Engineering & Technology | 2025 |
| 128 | tuned-collector-feedback-oscillator | Kommineni Manvitha Chowdary | Srm Institute Of Science And Technology | 2025 |
| 127 | 2×2 Vedic Multiplier using CMOS Logic | Vedasri J | Amrita Vishwa Vidyapeetham Coimbatore | 2025 |
| 126 | Low Noise amplifier design for mm wave | Sai Pratheep D | Sri Eshwar College Of Engineering | 2025 |
| 125 | Design and Simulation of a Wien-Bridge Oscillator for Stable Low-Distortion Sine Generation using eSim | Rajshree M | Vellore Institute Of Technology - Chennai | 2025 |
| 124 | Design and Simulation of an 8-Bit ALU Using Low-Power Adder Architectures in eSim | Harini Kamatchi Velrajan | Vellore Institute Of Technology | 2025 |
| 123 | TIME MARKER GENERATOR USING OPERATIONAL TRANSCONDUCTANCE AMPLIFIER | Karan Pratap Singh | Rajiv Gandhi Institute Of Petroleum Technology | 2025 |
| 122 | Stagger Tuned Amplifier | Sashrika T S | Sri Eshwar College Of Engineering Coimbatore | 2025 |
| 121 | Sallen Key Band Pass Filter | Thrishna M | Sri Eshwar College Of Engineering | 2025 |
| 120 | Ultrasonic Distance Sensor with Temperature Compensation using eSim | Shaunak Sagar Sirdesai | Sctr'S Pune Institute Of Computer Technology | 2025 |
| 119 | Wien bridge oscillator | Shazia Fahmeeda S | Sri Eshwar College Of Engineerig | 2025 |
| 118 | Design and Analysis of Current Mirror OTA in 0.18μm. | Moinuddin Ansari | Zakir Husain College Of Engineering And Technology | 2025 |
| 117 | Ultra-Low Power CMOS Voltage-Controlled Oscillator (VCO) for Autonomous Microsystems | Harini Js | Loyola-Icam College Of Engineering And Technology | 2025 |
| 116 | AC Voltage Control circuit using DIAC-TRIAC | Laksana A | Sri Eshwar College Of Engineering | 2025 |
| 115 | Design and Analysis of 4-bit and 8-bit Barrel Shifter using Integrated CMOS Technology | Jyothula Apparao | Vishnu Institute Of Technology | 2025 |
| 114 | Design and Simulation of a Full-Duplex UART (Transmitter + Receiver) | Dipali Wankhede | Shri Guru Gobind Singhji Institute Of Engineering And Technology, Vishnupuri, Nanded | 2025 |
| 113 | Study of Inverting and Non-Inverting Amplifiers with real time Application | K Nadhiya | Sri Eshwar College Of Engineering,coimbatore | 2025 |
| 112 | Designing State Variable Filter | Anuradha Ayyagary | Vit Bhopal | 2025 |
| 111 | Design and Analysis of Current Mirror circuits | Pindi Vishal | Dr B R Ambedhkar National Institute Of Technology, Jalandhar, Punjab | 2025 |
| 110 | Memristor-CMOS Hybrid Look-Up-Table Based Full Adder | Kh Pavithra | Rajiv Gandhi University Of Knowledge Technologies Rk Valley | 2025 |
| 109 | 4-bit Successive Approximation Register (SAR) ADC | K.neha | Sastra Deemed University | 2025 |
| 108 | Schilling, D. L., & Belove, C. (1998). Electronic Circuits: Discrete and Integrated. McGraw-Hill. | Krishna Kand S | Sri Eshwar College Of Engineering | 2025 |
| 107 | Shunt Voltage Regulator Using an Operational Amplifier | Asvitha Ms | Sri Eshwar College Of Engineering | 2025 |
| 106 | Design and Implementation of 4 Bit Carry Generator Circuit using Pass Transistor Logic with 2x1 Mux Approach | Nitish Kanna | Chennai Institute Of Technology | 2025 |
| 105 | Bootstrap Transimpedance Amplifier with adjustable capacitance | S H Atchaya | Sastra Deemed University | 2025 |
| 104 | Design and Migration of Colpitts Oscillator Using NPN Transistor in eSim | Asvitha Ms | Sri Eshwar College Of Engineering,coimatore | 2025 |
| 103 | Instrumentation Amplifier using AD620 IC in ESim | Ajiteshkumarsingh | Sir Chotu Ram Institute Of Engineeing & Technology | 2025 |
| 102 | Design and Simulation of an Op-Amp Based True RMS-to-DC Converter Using eSim | Ashwini | Sir Chhotu Ram Institute Of Engineering And Technology | 2025 |
| 101 | Delta Sigma Modulator | Sabareesh S | Sastra Deemed University | 2025 |
| 100 | Hazeltine Neutralised Oscillator | Arun Kumar P | Sri Eshwar College Of Engineering | 2025 |
| 99 | Multi-Stage Noise Shaping (MASH) Sigma-Delta ADC | Sudharsan Naytik. V | Meenakshi Sundararajan Engineering College | 2025 |
| 98 | Design and Simulation of a Precision Peak Detector Using Op-Amp circuit | Sanjay S | Meenakshi Sundararajan Engineering College | 2025 |
| 97 | Design Of an 18 Transistor Hybrid Flipflop with pass transistor logic | Pochaboina Vijayalaxmi | Cmr College Of Engineering & Technology | 2025 |
| 96 | Wien Bridge Oscillator using Transistor BJT | Krishna Mishra | Sir Chhotu Ram Institute Of Engineering Technology Meerut | 2025 |
| 95 | Design and Simulation of a 3-Bit Serial Adder Using Full Adder and D Flip-Flop in eSim | Nitin Chaudhary | J.k. Institute Of Applied Physics And Technology, University Of Allahabad. | 2025 |
| 94 | Migration of Switched-Capacitor Filter Design from Proprietary Tools to eSim | Radhika Ashvin Savaliya | Birla Vishvakarma Mahavidyalaya | 2025 |
| 93 | Implementation of logic OR using Memristors | Shivani R | Shanmugha Arts, Science, Technology & Research Academy | 2025 |
| 92 | Chebyshev Fifth Order Filter | Harikrishna R | Sastra Deemed University | 2025 |
| 91 | Simulation of Hartley Oscillator using Transistor in eSim | Akash Waliya | Sir Chhotu Ram Institute Of Engineering And Technology | 2025 |
| 90 | Output Capacitorless Low Dropout Regulator with Slew Rate Enhancement | Prithvi Natarajan | Sastra Deemed University, Thanjavur | 2025 |
| 89 | Design and Implementation of Tapped Coil Oscillator with Frequency Modulation | Yogeswaran I | Meenakshi Sundararajan Engineering College | 2025 |
| 88 | Dual-Edge Triggered D Flip-Flop for reduced dynamic power consumption | Prajeen | Meenakshi Sundararajan Engineering College | 2025 |
| 87 | Integrated Audio Processing System by using Class-D Amplifier with Filters and Modulation | Anurag Pal | Dr.ambedkar Institute Of Technology For Divyangjan,kanpur | 2025 |
| 86 | Design for a 2-bit calculator Using Digital Logic Gates | Arindam Konwar | Srm Institute Of Science And Technology Ncr Campus | 2025 |
| 85 | Active Twin-T Notch Filter | Kamalesh V | Sastra University | 2025 |
| 84 | Design and Implementation of an 8-bit Wallace Tree-Based Multiplier in VHDL | Kishor S.a | Chennai Institute Of Technology | 2025 |
| 83 | Design and Design and Analysis of a Novel Reversible Encoder/Decoder | Dev Dharsshan | Loyola-Icam College Of Engineering And Technology | 2025 |
| 82 | HIGH SPEED CMOS BASED 1:4 BIT DEMULTIPLEXER | L Sivasubramani | Loyola Icam College Of Engineering And Technology, Chennai | 2025 |
| 81 | Photonic-CMOS Hybrid Neural Network Processor | Kishor S.a | Chennai Institute Of Technology | 2025 |
| 80 | Low-Power Arithmetic Logic Unit (ALU) Design using Clock Gating | Vasipalli Sai Kiriti | Kalasalingam Academy Of Research And Education | 2025 |
| 79 | 8-bit Brent Kung for low power and low area consumption | Enugula Akash | Rajiv Gandhi University Of Knowledge Technologies | 2025 |
| 78 | 7 Transistor 2 Memristor Non Volatile SRAM | Tankala Srivedanarayana | Dr. Shyam Prasad Mukherjee International Institute Of Information Technology, Naya Raipur | 2025 |
| 77 | 16-Bit Arithmetic Logic Unit | K Shreeja | Indian Institute Of Information Technology, Guwahati | 2025 |
| 76 | Design and Implementation of Hardened Flip-Flop using eSim | Akshay Ajit Rukade | Indian Institute Of Technology Madras | 2025 |
| 75 | Design and Implementation of CMOS-based SRAM Memory Array using SVL Technique at 180nm/130nm/45nm Technology | Krushna Dinesh Rane | Indian Institute Of Technology Roorkee | 2025 |
| 74 | Design of Transconductance Amplifier. | Venkatajhalam S | Madras Institute Of Technoloy, Chennai. | 2025 |
| 73 | Sequence detector using fsm | Prakhar Kaushik | Ajay Kumar Garg Engineering Collage | 2025 |
| 72 | Design and Simulation of a Superheterodyne Receiver Using Analog Approximation of Discrete-Time Blocks in eSim | Mukta Pande | Jaypee Institute Of Information Technology | 2025 |
| 71 | A Design and Analysis of Op Amp Twin-T Band Reject Notch Filter | Arnav Maindola | Jaypee Institute Of Information Technology | 2025 |
| 70 | DESIGN OF SHIFT AND ADD MULTIPLIER | Vijay Kumar | St Martins Engineering College | 2025 |
| 69 | Flip Flops Overview | Kabir Patil | Spce | 2025 |
| 68 | Single-Cycle RISC-V Processor Implementation in eSim | Saiyam A. Bhansali | Institute Of Technology | 2025 |
| 67 | Design and Implementation of a Variable Output Buck-Boost DC-DC Converter | Revati Manohar Thoke | Government College Of Engineering, Karad. | 2025 |
| 66 | Op-Amp (741) Based Temperature to Voltage Converter for practical applications. | Ankit | Shri Mata Vaishno Devi University | 2025 |
| 65 | LOW POWER TECHNIQUE FOR FINFET DOMINO CKT | Agnihotram Vandana | Jntuh | 2025 |
| 64 | Design Automatic Transfer Switch using Mosfet | Abhishek Sharma | Shri Mata Vaishno Devi University | 2025 |
| 63 | Design and Implementation of a Low-Power, High-Performance Voltage Regulator Using IC7805 | Gowtham Lovely Kumari | St.martins Engineering College | 2025 |
| 62 | 6T SRAM Cell Design and Simulation using eSim | Rishabh Sharma | Punjab Engineering College | 2025 |
| 61 | Design and Implementation of a Low-Power, High-Performance Voltage Regulator Using IC7805 | Gowtham Lovely Kumari | St.martins Engineering College | 2025 |
| 60 | Logarithmic Amplifier using Operational Amplifier and Diode | Aarya Devendra Kulkarni | Chh. Shahu College Of Engineering | 2025 |
| 59 | Op-Amp Based Constant Amplitude Phase Filter | Keshav Kumar Choudhary | National Institute Of Technology Nagaland | 2025 |
| 58 | Smart Biomedical Signal Processing System | Sneha Gosain | Medical Education And Research Institute | 2025 |
| 57 | Design and Analysis of Class B Push-Pull Amplifier using esim. | Saksham Bhardwaj | Shri Mata Vaishno Devi University, Katra | 2025 |
| 56 | Design and Simulation of a Directional Seat Vibration Alert System for Obstacle Detection in Foggy Conditions using e Sim | Tamminaina Siva Kumar | Amrita Viswa Vidyapeetham,amritapuri | 2025 |
| 55 | Design and Simulation of 8-point FFT | Dayakar Satya Sai Jagata | National Institute Of Technology Karnataka,surathkal | 2025 |
| 54 | Design and Implementation of Reversible Logic Gates Using CMOS | Sruthi S | Sri Eshwar College Of Engineering | 2025 |
| 53 | Design and Implementation of Majority and Minority Circuits Using CMOS and RTL Logic | Sruthi S | Sri Eshwar College Of Engineering | 2025 |
| 52 | Design and Simulation of a Precision Temperature Sensor using Op-Amp Signal Conditioning Circuit | Srinivas Nv | Amrita School Of Engineering | 2025 |
| 51 | High-Speed Low-Power Approximate 4:2 Compressor | Theetla Sirisha | Rajiv Gandhi University Of Knowledge Technologies, Srikakulam | 2025 |
| 50 | Hybrid CMOS Memristor based One-bit binary comparator | Sanjay Jacob Williams | Vel Tech Multi Tech Dr. Rangarajan Dr. Sakunthala Engineering College. | 2025 |
| 49 | Transformer-Coupled Class A Power Amplifiers | Dhruv Sharma | Shri Mata Vaishno Devi University | 2025 |
| 48 | Pseudo-Random Binary Sequence (PRBS) Generator Simulation | Debopam Roy | National Institute Of Electronics And Information Technology, Aurangabad | 2025 |
| 47 | ENERGY EFFICIENT DYNAMIC TERNARY FLIP FLOP FOR LOW POWER VLSI APPLICATIONS | Gurijala Yatheendra Reddy | Indian Institute Of Information Technology Kottayam | 2025 |
| 46 | Fault-Tolerant Approximate Ternary Full Adder | Monish Alavalapati | Indian Institute Of Information Technology, Kottayam | 2025 |
| 45 | Single Stage and Two Stage OP-AMP Design in 180nm CMOS Technology | Krishendu Roy | National Institute Of Technology Rourkela | 2025 |
| 44 | Comparative Power Analysis of CMOS & Adiabatic Logic Gates | Kondeti Chirunadh | Jntuh College Of Engineering Sultanpur | 2025 |
| 43 | Recents trends on mosfet based cascode current mirrors | Kuruva Harinath | Rajiv Gandhi University Of Knowledge And Technologies - Rk Valley Kadapa | 2025 |
| 42 | Design and Simulation of a Boost Converter for LED Lighting Applications | Abdullah Najam | Indian Institute Of Engineering Science And Technology, Shibpur | 2025 |
| 41 | Design and Simulation of Low Power 8 x 1 Multiplexer using Transmission gates | Pranav Vinod Indurkar | Pune Institute Of Computer Technology | 2025 |
| 40 | Implementation of a three-channel DC-DC synchronous buck converter using 4H-SiC CMOS technology | Supriyo Roy | Indian Institute Of Engineering Science And Technology, Shibpur | 2025 |
| 39 | Switched-Capacitor DC-DC Converter | Abhay Kumar Srivastava | Indian Institute Of Technology(bhu) Varanasi | 2025 |
| 38 | Reconfigurable Dual-Band CMOS RF Mixer for Software-Defined Radio Applications | Aditya Raj | Drexel University, Usa | 2025 |
| 37 | Design and Simulation of a 5-Transistor Unidirectional Thermometer Code Latch | Mehtab Shaik | Vnr Vjiet | 2025 |
| 36 | Design and Simulation of a High-Speed, Low-Power CMOS Inverter for Digital Logic Applications in eSim | Elango S | Kongu Engineering College | 2025 |
| 35 | A CMOS-Based Voltage-Controlled Oscillator (VCO) for Wireless Applications Using eSim | Kavin P | Kongu Enginnering College | 2025 |
| 34 | Efficient 28 nm CMOS Serial-to-Parallel Converter for 5G Systems | Mohammad Shahul | Aditya College Of Engineering And Technology | 2025 |
| 33 | Amplification of weak electrical signals using a common emitter amplifier and verification of current and voltage gain | J.a Jenie Shalin | Easwari Engineering College | 2025 |
| 32 | PWM DC Motor Driver for Speed Control | Kavitha Kamaraj | Jaya Engineering College | 2025 |
| 31 | Regulated power supply with a transistor -based voltage regulation | Gokulnath P | Rajalakshmi Institute Of Technology,chennai | 2025 |
| 30 | A Verilog Model of Adaptable Traffic Control System Using Mealy State Machines | Hamim Reja | Aliah University | 2025 |
| 29 | Design and Implementation of a 1-Bit Comparator Using CMOS Logic | Saravanakumar M | Sri Eshwar College Of Engineering | 2025 |
| 28 | Design of a Self-Oscillating Boost Power Factor Correction Converter | Vaibhav Revankar | Sjb Institute Of Technology | 2025 |
| 27 | Design and Analysis of BiCMOS Operational Amplifiers | Vijith S | Sjb Institute Of Technology | 2025 |
| 26 | Automatic Solar Tracking System Using LDR and Comparator | Shivaraman T | Vellore Institute Of Technology, Bhopal | 2025 |
| 25 | ACTIVE NOISE CANCELLATION USING OP-AMP | Simon Jai S R | Sri Eshwar College Of Engineering | 2025 |
| 24 | Phone Ring Amplifier | Nachiketh G | Sjbit | 2025 |
| 23 | Design of High PSRR Folded Cascode Operational Amplifier for LDO application | Bibekananda Pradhan | Veer Surendra Sai University Of Technology, Burla | 2025 |
| 22 | Design and implementation of general purpose opamp using multipath frequency compensation | Bidhan Biswas | Rajiv Gandhi Institute Of Petrolium Technology | 2025 |
| 21 | Mobile Network Jammer | Shrirang Rekhate | Shri Guru Gobind Singhji Institute Of Engineering And Technology, Nanded | 2025 |
| 20 | Novel Op-Amp Based LC Oscillator for Wireless Communications | Krishnendu Roy | National Institute Of Technology Rourkela | 2024 |
| 19 | Optimizing Current Gain of a Darlington Amplifier | Aravind S | Sastra | 2024 |
| 18 | CMOS SR Latch (NOR-based design using Static CMOS Logic) , Cascode Current Mirror (MOSFET-based) | Mrunal Virendra Bapardekar | Kj Somiaya School Of Engineering | 2024 |
| 17 | Novel passive negative and positive champer circuit | Mohamed Niyash S | St. Xavier’s Catholic College Of Engineering | 2024 |
| 16 | ANALYSIS OF 7805 VOLTAGE REGULATORS IN ELECTRONIC CIRCUIT | Suji V | Rajalakshmi Institute Of Technology | 2024 |
| 15 | IMPLEMENTATION OF PARALLEL ADDER USING 180nm TECHNOLOGY | Abul Hasan | Aliah University | 2024 |
| 14 | Current Source Circuit Using Power MOSFET | Kunal Subhash Khandalkar | Loknete Shamrao Peje Government College Of Engineering, Ratnagiri | 2024 |
| 13 | LED Flasher Circuits Using the 555 Timer IC | Aditya Ade | Shri Guru Gobind Singhji Institute Of Engineering & Technology Vishnupuri, Nanded - 431606 (ms) | 2024 |
| 12 | Design and Simulation of an Astable Multivibrator using a 555 Timer IC | Antony Aakash S | St Xavier'S Catholic College Of Engineering, Kanyakumari | 2024 |
| 11 | DESIGN AND ANALYSIS OF A PHOTODIODE AMPLIFIER CIRCUIT (TRANSIMPEDANCE CIRCUIT) USING OP-AMP LM741 USING eSIM | Maanit Arora | Delhi Technological University | 2024 |
| 10 | A STUDY ON SINGLE PHASE FULL WAVE UNCONTROLLED RECTIFIED WITH AN R-LOAD | Rohan V S | Rajalakshmi Institute Of Technology | 2024 |
| 9 | Design and simulation of Unity Gain Inverter using eSim | Dhananjay Umesh Walchale | Shri Guru Gobind Singhji Institute Of Engineering And Technology Nanded | 2024 |
| 8 | Phase-Locked Loop (PLL) Circuit for Frequency Synthesis | Rohan Chanana | Delhi Technological University | 2024 |
| 7 | Design and Analysis of Tow Thomas Biquad Filter | Prajwal Singh | Netaji Subhas University Of Technology | 2024 |
| 6 | Simulation and Frequency Response Analysis of a Wien Bridge Oscillator using eSim | Divyam Goyal | Punjab Engineering College (deemed To Be University), Chandigarh | 2024 |
| 5 | Chaos Circuit | Vivek Kumar | Shri Mata Vaishno Devi University | 2024 |
| 4 | Simple Up/down Fading Led Circuit Using 555 timer ic | Bipin Kumar | Shri Mata Vaishno Devi University | 2024 |
| 3 | Design and Simulation of frequency divider circuit | Arun Pandiyan P B | Karpagam College Of Engineering | 2024 |
| 2 | Optimal design of Twin-T notch filter using eSim | Nameera Jabi | Jamia Millia Islamia | 2024 |
| 1 | A 180 nm Low-Cost Operational Amplifier for IoT Applications | Krishan Kumar | National Institute Of Technology, Agartala | 2024 |