Research Migration in Progress
Work is in progress for the following submissions under the Research Migration Project
| No | Research Migration Project | Contributor Name | Institute | Year |
|---|---|---|---|---|
| 176 | Automatic Water Pump Control Circuit based on Sequential Logic (SR Latch) | M.mathi Malar | Sastra Deemed University | 2025 |
| 175 | 4-bit Baugh-Wooley Multiplier | Jovin P John | Albertian Institute Of Science And Technology | 2025 |
| 174 | Latch Comparator with adjustable Hysteresis using eSim | Jitheshkrishna R | Chennai Institute Of Technology | 2025 |
| 173 | Universal shift register with low power consumption | Virutchika K | Sastra Deemed University | 2025 |
| 172 | Simulation of Phase Shift Oscillator | N Misazhini | Sastra Deemed University | 2025 |
| 171 | Design and Analysis of a Low Dropout Voltage Regulator in 130nm technology node | Md Ghalib Hussain | Zakir Husain College Of Engineering And Technology | 2025 |
| 170 | DESIGN AND ANALYSIS OF A FUNCTION GENERATOR USING OP-AMP in eSIM | Bolem Divya Sri | Karunya Institue Of Technology And Sciences | 2025 |
| 169 | Simulation of Analog multiplier circuit using eSim | Jawaji Jerusha Angeline | Karunya Institue Of Technology And Sciences | 2025 |
| 168 | Frequency To Voltage Converter Using 555n | Rajasri Kutikuppala | Indian Institute Of Information Technology , Sri City | 2025 |
| 167 | To design and construct Monostable multivibrator using op amp | M.niveditha | Karunya Institue Of Technology And Sciences | 2025 |
| 166 | Timer Circuit Using OTRA and its Application as Astable and MonostableMultivibrator using esim | Neeraj G | Chennai Institute Of Technology | 2025 |
| 165 | Common emitter amplifier with voltage divider bias | Hari Haran V | Vel Tech Multi Tech Dr.rangarajan Dr.sakunthala Engineering College(autonomous) | 2025 |
| 164 | DESIGN OF A LOW-POWER SHIFT REGISTER WITH FINE-GRAINED CLOCK GATING IN ESIM | Gautam Suresh | Chennai Institute Of Technology | 2025 |
| 163 | Design and Simulation of a Power-Efficient 16:1 Multiplexer Using TGL with Power Gating | Deepak Prabakaran | Chennai Institute Of Technology | 2025 |
| 162 | TWO-STAGE BJT AMPLIFIER. | Deepeshkumar A | Vel Tech Multi Tech Dr.rangarajan Dr.sakunthala Engineering College(autonomous) | 2025 |
| 161 | Down-Conversion Mixer Design | Priyanshu Kumar | Shri Mata Vaishno Devi University Katra Jammu & Kashmir | 2025 |
| 160 | Analysis and Design of a Double Tuned Clapp Oscillator for Multi-Band Multi-Standard Radio | Panshul Rastogi | Hindustan College Of Science And Technology (hcst) Mathura | 2025 |
| 159 | Passive-Linearized CMOS Class-AB Power Amplifier for BLE 4.0 | Prahas | Hindustan College Of Science And Technology | 2025 |
| 158 | IMPLEMENTATION OF SIMPLIFIED MOS-ONLY LOW-VOLTAGE BANDGAP REFERENCE IN ESIM | Merlin Jennifer S | Chennai Institute Of Technology | 2025 |
| 157 | Design, Simulation, and Performance Analysis of an 8-bit Successive Approximation Register (SAR) Analog-to-Digital Converter | Tatikonda Ramakrishna | Chennai Institute Of Technology | 2025 |
| 156 | To design a class-C power amplifier (low power) that could be potentially used for biomedical applications such as medical implants and smart wearable | Ayutansh Sharma | Hindustan College Of Science And Technology | 2025 |
| 155 | IMPLEMENTATION OF 4-BIT MAGNITUDE COMPARATOR IN ESIM | Ramaprakash B | Chennai Institute Of Technology | 2025 |
| 154 | IMPLEMENTATION OF 4-BIT BINARY COMPARATOR USING OPTIMIZED 12T LOGIC IN ESIM | Edna Joy J | Chennai Institute Of Technology | 2025 |
| 153 | Design and analysis of single stage amplifier | Harini M V | Sri Eshwar College Of Engineering | 2025 |
| 152 | Optimized 4-Bit Binary-to-Gray Code Converter for VLSI Applications Using MUX-XOR Design | Priyadharsan D | Chennai Insitute Of Technology | 2025 |
| 151 | IMPLEMENTATION OF 5-TRANSISTOR (5T) LATCH USING OPTIMIZED TRANSISTOR COUNT IN ESIM | Santhosh C | Chennai Institute Of Technology | 2025 |
| 150 | Multiplexer-Based Implementation of Digital Adder Circuits using eSim | Senthil Kumar Mahalingam | Chennai Institute Of Technology | 2025 |
| 149 | IMPLEMENTATION OF A CONFIGURABLE FLIP-FLOP (D-FF / SR-FF) WITH MODE SELECT IN ESIM | S S Jhotheeshwar | Chennai Institute Of Technology | 2025 |
| 148 | Design and Simulation of a First-Order Sigma-Delta (ΔΣ) ADC with Digital Decimation in eSim | Gouri Saxena | Vit Bhopal | 2025 |
| 147 | Design of an Analog Front-End for ECG Signal Conditioning | Krisanth M | Chennai Institute Of Technology | 2025 |
| 146 | IMPLEMENTATION OF MODIFIED CARRY SELECT ADDER USING BINARY EXCESS-1 CONVERTER IN ESIM | Yogavelan M D | Chennai Institute Of Technology | 2025 |
| 145 | Efficient High-Side N-Channel MOSFET Driver Circuit | Nithishwaran S | Sri Eshwar College Of Engineering | 2025 |
| 144 | IMPLEMENTATION OF TWO-STAGE CASCODED OTA BASED LOW-DROPOUT (LDO) VOLTAGE REGULATOR IN ESIM | Praveen R | Chennai Institute Of Technology | 2025 |
| 143 | 4-bit R-2R Ladder Digital-to-Analog Converter | Karthick Naveen S | Sri Eshwar College Of Engineering | 2025 |
| 142 | IMPLEMENTATION OF 4-BIT GRAY-CODE COUNTER USING BINARY COUNTER AND XOR-ONLY BINARY→GRAY CONVERTER IN ESIM | Priyadharsan Dhanasekar | Chennai Insitute Of Technology | 2025 |
| 141 | 3-Bit Majority Function & LZS | Rupesh Nawin S | Sri Eshwar College Of Engineering | 2025 |
| 140 | Implementation of 4-Bit Ripple Carry Adder Using Optimized 10T Full Adder in eSim | Senbagaseelan V | Chennai Institute Of Technology | 2025 |
| 139 | Design and Analysis of Temperature Compensated Log Amplifier Using Op-Amp and Diode | Karthiban S T | Sri Eshwar College Of Engineering | 2025 |
| 138 | RISC-V Mini CPU Design and Simulation | Malothu Anil Kumar | Cmr College Of Engineering & Technology | 2025 |
| 137 | tuned-collector-feedback-oscillator | Kommineni Manvitha Chowdary | Srm Institute Of Science And Technology | 2025 |
| 136 | 2×2 Vedic Multiplier using CMOS Logic | Vedasri J | Amrita Vishwa Vidyapeetham Coimbatore | 2025 |
| 135 | A Full Parallel Priority Encoder Design Using Esim | Shylash.s | Chennai Institute Of Technology | 2025 |
| 134 | Low Noise amplifier design for mm wave | Sai Pratheep D | Sri Eshwar College Of Engineering | 2025 |
| 133 | Design and Simulation of a Wien-Bridge Oscillator for Stable Low-Distortion Sine Generation using eSim | Rajshree M | Vellore Institute Of Technology - Chennai | 2025 |
| 132 | Design and Simulation of an 8-Bit ALU Using Low-Power Adder Architectures in eSim | Harini Kamatchi Velrajan | Vellore Institute Of Technology | 2025 |
| 131 | TIME MARKER GENERATOR USING OPERATIONAL TRANSCONDUCTANCE AMPLIFIER | Karan Pratap Singh | Rajiv Gandhi Institute Of Petroleum Technology | 2025 |
| 130 | Stagger Tuned Amplifier | Sashrika T S | Sri Eshwar College Of Engineering Coimbatore | 2025 |
| 129 | Sallen Key Band Pass Filter | Thrishna M | Sri Eshwar College Of Engineering | 2025 |
| 128 | Ultrasonic Distance Sensor with Temperature Compensation using eSim | Shaunak Sagar Sirdesai | Sctr'S Pune Institute Of Computer Technology | 2025 |
| 127 | Wien bridge oscillator | Shazia Fahmeeda S | Sri Eshwar College Of Engineerig | 2025 |
| 126 | Design and Analysis of Current Mirror OTA in 0.18μm. | Moinuddin Ansari | Zakir Husain College Of Engineering And Technology | 2025 |
| 125 | Ultra-Low Power CMOS Voltage-Controlled Oscillator (VCO) for Autonomous Microsystems | Harini Js | Loyola-Icam College Of Engineering And Technology | 2025 |
| 124 | AC Voltage Control circuit using DIAC-TRIAC | Laksana A | Sri Eshwar College Of Engineering | 2025 |
| 123 | Design and Analysis of 4-bit and 8-bit Barrel Shifter using Integrated CMOS Technology | Jyothula Apparao | Vishnu Institute Of Technology | 2025 |
| 122 | Design and Simulation of a Full-Duplex UART (Transmitter + Receiver) | Dipali Wankhede | Shri Guru Gobind Singhji Institute Of Engineering And Technology, Vishnupuri, Nanded | 2025 |
| 121 | Study of Inverting and Non-Inverting Amplifiers with real time Application | K Nadhiya | Sri Eshwar College Of Engineering,coimbatore | 2025 |
| 120 | Designing State Variable Filter | Anuradha Ayyagary | Vit Bhopal | 2025 |
| 119 | Design and Analysis of Current Mirror circuits | Pindi Vishal | Dr B R Ambedhkar National Institute Of Technology, Jalandhar, Punjab | 2025 |
| 118 | Memristor-CMOS Hybrid Look-Up-Table Based Full Adder | Kh Pavithra | Rajiv Gandhi University Of Knowledge Technologies Rk Valley | 2025 |
| 117 | 4-bit Successive Approximation Register (SAR) ADC | K.neha | Sastra Deemed University | 2025 |
| 116 | Schilling, D. L., & Belove, C. (1998). Electronic Circuits: Discrete and Integrated. McGraw-Hill. | Krishna Kand S | Sri Eshwar College Of Engineering | 2025 |
| 115 | Shunt Voltage Regulator Using an Operational Amplifier | Asvitha Ms | Sri Eshwar College Of Engineering | 2025 |
| 114 | Design and Implementation of 4 Bit Carry Generator Circuit using Pass Transistor Logic with 2x1 Mux Approach | Nitish Kanna | Chennai Institute Of Technology | 2025 |
| 113 | Bootstrap Transimpedance Amplifier with adjustable capacitance | S H Atchaya | Sastra Deemed University | 2025 |
| 112 | Design and Migration of Colpitts Oscillator Using NPN Transistor in eSim | Asvitha Ms | Sri Eshwar College Of Engineering,coimatore | 2025 |
| 111 | coordinate rotation digital computer - (CORDIC algorithm for computing trigonometric and hyperbolic functions) | Mohan Krishna Sikhakolli | Rajiv Gandhi University Of Knowledge Technoligies, Nuzvid | 2025 |
| 110 | Instrumentation Amplifier using AD620 IC in ESim | Ajiteshkumarsingh | Sir Chotu Ram Institute Of Engineeing & Technology | 2025 |
| 109 | Design and Simulation of an Op-Amp Based True RMS-to-DC Converter Using eSim | Ashwini | Sir Chhotu Ram Institute Of Engineering And Technology | 2025 |
| 108 | Delta Sigma Modulator | Sabareesh S | Sastra Deemed University | 2025 |
| 107 | Hazeltine Neutralised Oscillator | Arun Kumar P | Sri Eshwar College Of Engineering | 2025 |
| 106 | Multi-Stage Noise Shaping (MASH) Sigma-Delta ADC | Sudharsan Naytik. V | Meenakshi Sundararajan Engineering College | 2025 |
| 105 | Design and Simulation of a Precision Peak Detector Using Op-Amp circuit | Sanjay S | Meenakshi Sundararajan Engineering College | 2025 |
| 104 | Design and Simulation of a Precision Peak Detector Using Op-Amp circuit | Sanjay S | Meenakshi Sundararajan Engineering College | 2025 |
| 103 | Design Of an 18 Transistor Hybrid Flipflop with pass transistor logic | Pochaboina Vijayalaxmi | Cmr College Of Engineering & Technology | 2025 |
| 102 | Wien Bridge Oscillator using Transistor BJT | Krishna Mishra | Sir Chhotu Ram Institute Of Engineering Technology Meerut | 2025 |
| 101 | Design and Simulation of a 3-Bit Serial Adder Using Full Adder and D Flip-Flop in eSim | Nitin Chaudhary | J.k. Institute Of Applied Physics And Technology, University Of Allahabad. | 2025 |
| 100 | Migration of Switched-Capacitor Filter Design from Proprietary Tools to eSim | Radhika Ashvin Savaliya | Birla Vishvakarma Mahavidyalaya | 2025 |
| 99 | Implementation of logic OR using Memristors | Shivani R | Shanmugha Arts, Science, Technology & Research Academy | 2025 |
| 98 | Chebyshev Fifth Order Filter | Harikrishna R | Sastra Deemed University | 2025 |
| 97 | A Highly Linear Low Power Envelope Detector | Priyanka | Dronacharya Group Of Institutions | 2025 |
| 96 | Design and Simulation of an Inverting R-2R Ladder DAC using eSim | Vanna Nilavan Mani | Meenakshi Sundararajan Engineering College | 2025 |
| 95 | Simulation of Hartley Oscillator using Transistor in eSim | Akash Waliya | Sir Chhotu Ram Institute Of Engineering And Technology | 2025 |
| 94 | Output Capacitorless Low Dropout Regulator with Slew Rate Enhancement | Prithvi Natarajan | Sastra Deemed University, Thanjavur | 2025 |
| 93 | Design and Implementation of Tapped Coil Oscillator with Frequency Modulation | Yogeswaran I | Meenakshi Sundararajan Engineering College | 2025 |
| 92 | Dual-Edge Triggered D Flip-Flop for reduced dynamic power consumption | Prajeen | Meenakshi Sundararajan Engineering College | 2025 |
| 91 | Design and Realization of a Ripple-Controlled Active Chebyshev Filter using Sallen-Key Topology in eSim | Yogeswaran I | Meenakshi Sundararajan Engineering College | 2025 |
| 90 | Integrated Audio Processing System by using Class-D Amplifier with Filters and Modulation | Anurag Pal | Dr.ambedkar Institute Of Technology For Divyangjan,kanpur | 2025 |
| 89 | Design for a 2-bit calculator Using Digital Logic Gates | Arindam Konwar | Srm Institute Of Science And Technology Ncr Campus | 2025 |
| 88 | Active Twin-T Notch Filter | Kamalesh V | Sastra University | 2025 |
| 87 | Design and Implementation of an 8-bit Wallace Tree-Based Multiplier in VHDL | Kishor S.a | Chennai Institute Of Technology | 2025 |
| 86 | Design and Implementation of 8-bit Succesive Approximation Register ADC. | Manwantha Krishnan | Meenakshi Sundararajan Engineering College | 2025 |
| 85 | Design and Design and Analysis of a Novel Reversible Encoder/Decoder | Dev Dharsshan | Loyola-Icam College Of Engineering And Technology | 2025 |
| 84 | Fast Response Voltage-to-Frequency Converter. | Rajasri Kutikuppala | Indian Institute Of Information Technology, Sri City | 2025 |
| 83 | HIGH SPEED CMOS BASED 1:4 BIT DEMULTIPLEXER | L Sivasubramani | Loyola Icam College Of Engineering And Technology, Chennai | 2025 |
| 82 | Photonic-CMOS Hybrid Neural Network Processor | Kishor S.a | Chennai Institute Of Technology | 2025 |
| 81 | Design of a Compact On-Chip Static IR Drop Detector System | Sakshi Pandey | Dronacharya Group Of Institutions Greater Noida | 2025 |
| 80 | Low-Power Arithmetic Logic Unit (ALU) Design using Clock Gating | Vasipalli Sai Kiriti | Kalasalingam Academy Of Research And Education | 2025 |
| 79 | 8-bit Brent Kung for low power and low area consumption | Enugula Akash | Rajiv Gandhi University Of Knowledge Technologies | 2025 |
| 78 | 7 Transistor 2 Memristor Non Volatile SRAM | Tankala Srivedanarayana | Dr. Shyam Prasad Mukherjee International Institute Of Information Technology, Naya Raipur | 2025 |
| 77 | 16-Bit Arithmetic Logic Unit | K Shreeja | Indian Institute Of Information Technology, Guwahati | 2025 |
| 76 | Design and Implementation of Hardened Flip-Flop using eSim | Akshay Ajit Rukade | Indian Institute Of Technology Madras | 2025 |
| 75 | Design and Implementation of CMOS-based SRAM Memory Array using SVL Technique at 180nm/130nm/45nm Technology | Krushna Dinesh Rane | Indian Institute Of Technology Roorkee | 2025 |
| 74 | Design of Transconductance Amplifier. | Venkatajhalam S | Madras Institute Of Technoloy, Chennai. | 2025 |
| 73 | Sequence detector using fsm | Prakhar Kaushik | Ajay Kumar Garg Engineering Collage | 2025 |
| 72 | Design and Simulation of a Superheterodyne Receiver Using Analog Approximation of Discrete-Time Blocks in eSim | Mukta Pande | Jaypee Institute Of Information Technology | 2025 |
| 71 | A Design and Analysis of Op Amp Twin-T Band Reject Notch Filter | Arnav Maindola | Jaypee Institute Of Information Technology | 2025 |
| 70 | DESIGN OF SHIFT AND ADD MULTIPLIER | Vijay Kumar | St Martins Engineering College | 2025 |
| 69 | Flip Flops Overview | Kabir Patil | Spce | 2025 |
| 68 | Single-Cycle RISC-V Processor Implementation in eSim | Saiyam A. Bhansali | Institute Of Technology | 2025 |
| 67 | Design and Implementation of a Variable Output Buck-Boost DC-DC Converter | Revati Manohar Thoke | Government College Of Engineering, Karad. | 2025 |
| 66 | Op-Amp (741) Based Temperature to Voltage Converter for practical applications. | Ankit | Shri Mata Vaishno Devi University | 2025 |
| 65 | LOW POWER TECHNIQUE FOR FINFET DOMINO CKT | Agnihotram Vandana | Jntuh | 2025 |
| 64 | Design Automatic Transfer Switch using Mosfet | Abhishek Sharma | Shri Mata Vaishno Devi University | 2025 |
| 63 | Design and Implementation of a Low-Power, High-Performance Voltage Regulator Using IC7805 | Gowtham Lovely Kumari | St.martins Engineering College | 2025 |
| 62 | 6T SRAM Cell Design and Simulation using eSim | Rishabh Sharma | Punjab Engineering College | 2025 |
| 61 | Design and Implementation of a Low-Power, High-Performance Voltage Regulator Using IC7805 | Gowtham Lovely Kumari | St.martins Engineering College | 2025 |
| 60 | Logarithmic Amplifier using Operational Amplifier and Diode | Aarya Devendra Kulkarni | Chh. Shahu College Of Engineering | 2025 |
| 59 | Op-Amp Based Constant Amplitude Phase Filter | Keshav Kumar Choudhary | National Institute Of Technology Nagaland | 2025 |
| 58 | Smart Biomedical Signal Processing System | Sneha Gosain | Medical Education And Research Institute | 2025 |
| 57 | Design and Analysis of Class B Push-Pull Amplifier using esim. | Saksham Bhardwaj | Shri Mata Vaishno Devi University, Katra | 2025 |
| 56 | Design and Simulation of a Directional Seat Vibration Alert System for Obstacle Detection in Foggy Conditions using e Sim | Tamminaina Siva Kumar | Amrita Viswa Vidyapeetham,amritapuri | 2025 |
| 55 | Design and Simulation of 8-point FFT | Dayakar Satya Sai Jagata | National Institute Of Technology Karnataka,surathkal | 2025 |
| 54 | Design and Implementation of Reversible Logic Gates Using CMOS | Sruthi S | Sri Eshwar College Of Engineering | 2025 |
| 53 | Design and Implementation of Majority and Minority Circuits Using CMOS and RTL Logic | Sruthi S | Sri Eshwar College Of Engineering | 2025 |
| 52 | Design and Simulation of a Precision Temperature Sensor using Op-Amp Signal Conditioning Circuit | Srinivas Nv | Amrita School Of Engineering | 2025 |
| 51 | High-Speed Low-Power Approximate 4:2 Compressor | Theetla Sirisha | Rajiv Gandhi University Of Knowledge Technologies, Srikakulam | 2025 |
| 50 | Hybrid CMOS Memristor based One-bit binary comparator | Sanjay Jacob Williams | Vel Tech Multi Tech Dr. Rangarajan Dr. Sakunthala Engineering College. | 2025 |
| 49 | Transformer-Coupled Class A Power Amplifiers | Dhruv Sharma | Shri Mata Vaishno Devi University | 2025 |
| 48 | Pseudo-Random Binary Sequence (PRBS) Generator Simulation | Debopam Roy | National Institute Of Electronics And Information Technology, Aurangabad | 2025 |
| 47 | ENERGY EFFICIENT DYNAMIC TERNARY FLIP FLOP FOR LOW POWER VLSI APPLICATIONS | Gurijala Yatheendra Reddy | Indian Institute Of Information Technology Kottayam | 2025 |
| 46 | Fault-Tolerant Approximate Ternary Full Adder | Monish Alavalapati | Indian Institute Of Information Technology, Kottayam | 2025 |
| 45 | Single Stage and Two Stage OP-AMP Design in 180nm CMOS Technology | Krishendu Roy | National Institute Of Technology Rourkela | 2025 |
| 44 | Comparative Power Analysis of CMOS & Adiabatic Logic Gates | Kondeti Chirunadh | Jntuh College Of Engineering Sultanpur | 2025 |
| 43 | Recents trends on mosfet based cascode current mirrors | Kuruva Harinath | Rajiv Gandhi University Of Knowledge And Technologies - Rk Valley Kadapa | 2025 |
| 42 | Design and Simulation of a Boost Converter for LED Lighting Applications | Abdullah Najam | Indian Institute Of Engineering Science And Technology, Shibpur | 2025 |
| 41 | Design and Simulation of Low Power 8 x 1 Multiplexer using Transmission gates | Pranav Vinod Indurkar | Pune Institute Of Computer Technology | 2025 |
| 40 | Implementation of a three-channel DC-DC synchronous buck converter using 4H-SiC CMOS technology | Supriyo Roy | Indian Institute Of Engineering Science And Technology, Shibpur | 2025 |
| 39 | Switched-Capacitor DC-DC Converter | Abhay Kumar Srivastava | Indian Institute Of Technology(bhu) Varanasi | 2025 |
| 38 | Reconfigurable Dual-Band CMOS RF Mixer for Software-Defined Radio Applications | Aditya Raj | Drexel University, Usa | 2025 |
| 37 | Design and Simulation of a 5-Transistor Unidirectional Thermometer Code Latch | Mehtab Shaik | Vnr Vjiet | 2025 |
| 36 | Design and Simulation of a High-Speed, Low-Power CMOS Inverter for Digital Logic Applications in eSim | Elango S | Kongu Engineering College | 2025 |
| 35 | A CMOS-Based Voltage-Controlled Oscillator (VCO) for Wireless Applications Using eSim | Kavin P | Kongu Enginnering College | 2025 |
| 34 | Efficient 28 nm CMOS Serial-to-Parallel Converter for 5G Systems | Mohammad Shahul | Aditya College Of Engineering And Technology | 2025 |
| 33 | Amplification of weak electrical signals using a common emitter amplifier and verification of current and voltage gain | J.a Jenie Shalin | Easwari Engineering College | 2025 |
| 32 | PWM DC Motor Driver for Speed Control | Kavitha Kamaraj | Jaya Engineering College | 2025 |
| 31 | Regulated power supply with a transistor -based voltage regulation | Gokulnath P | Rajalakshmi Institute Of Technology,chennai | 2025 |
| 30 | A Verilog Model of Adaptable Traffic Control System Using Mealy State Machines | Hamim Reja | Aliah University | 2025 |
| 29 | Design and Implementation of a 1-Bit Comparator Using CMOS Logic | Saravanakumar M | Sri Eshwar College Of Engineering | 2025 |
| 28 | Design of a Self-Oscillating Boost Power Factor Correction Converter | Vaibhav Revankar | Sjb Institute Of Technology | 2025 |
| 27 | Design and Analysis of BiCMOS Operational Amplifiers | Vijith S | Sjb Institute Of Technology | 2025 |
| 26 | Automatic Solar Tracking System Using LDR and Comparator | Shivaraman T | Vellore Institute Of Technology, Bhopal | 2025 |
| 25 | ACTIVE NOISE CANCELLATION USING OP-AMP | Simon Jai S R | Sri Eshwar College Of Engineering | 2025 |
| 24 | Phone Ring Amplifier | Nachiketh G | Sjbit | 2025 |
| 23 | Design of High PSRR Folded Cascode Operational Amplifier for LDO application | Bibekananda Pradhan | Veer Surendra Sai University Of Technology, Burla | 2025 |
| 22 | Design and implementation of general purpose opamp using multipath frequency compensation | Bidhan Biswas | Rajiv Gandhi Institute Of Petrolium Technology | 2025 |
| 21 | Mobile Network Jammer | Shrirang Rekhate | Shri Guru Gobind Singhji Institute Of Engineering And Technology, Nanded | 2025 |
| 20 | Novel Op-Amp Based LC Oscillator for Wireless Communications | Krishnendu Roy | National Institute Of Technology Rourkela | 2024 |
| 19 | Optimizing Current Gain of a Darlington Amplifier | Aravind S | Sastra | 2024 |
| 18 | CMOS SR Latch (NOR-based design using Static CMOS Logic) , Cascode Current Mirror (MOSFET-based) | Mrunal Virendra Bapardekar | Kj Somiaya School Of Engineering | 2024 |
| 17 | Novel passive negative and positive champer circuit | Mohamed Niyash S | St. Xavier’s Catholic College Of Engineering | 2024 |
| 16 | ANALYSIS OF 7805 VOLTAGE REGULATORS IN ELECTRONIC CIRCUIT | Suji V | Rajalakshmi Institute Of Technology | 2024 |
| 15 | IMPLEMENTATION OF PARALLEL ADDER USING 180nm TECHNOLOGY | Abul Hasan | Aliah University | 2024 |
| 14 | Current Source Circuit Using Power MOSFET | Kunal Subhash Khandalkar | Loknete Shamrao Peje Government College Of Engineering, Ratnagiri | 2024 |
| 13 | LED Flasher Circuits Using the 555 Timer IC | Aditya Ade | Shri Guru Gobind Singhji Institute Of Engineering & Technology Vishnupuri, Nanded - 431606 (ms) | 2024 |
| 12 | Design and Simulation of an Astable Multivibrator using a 555 Timer IC | Antony Aakash S | St Xavier'S Catholic College Of Engineering, Kanyakumari | 2024 |
| 11 | DESIGN AND ANALYSIS OF A PHOTODIODE AMPLIFIER CIRCUIT (TRANSIMPEDANCE CIRCUIT) USING OP-AMP LM741 USING eSIM | Maanit Arora | Delhi Technological University | 2024 |
| 10 | A STUDY ON SINGLE PHASE FULL WAVE UNCONTROLLED RECTIFIED WITH AN R-LOAD | Rohan V S | Rajalakshmi Institute Of Technology | 2024 |
| 9 | Design and simulation of Unity Gain Inverter using eSim | Dhananjay Umesh Walchale | Shri Guru Gobind Singhji Institute Of Engineering And Technology Nanded | 2024 |
| 8 | Phase-Locked Loop (PLL) Circuit for Frequency Synthesis | Rohan Chanana | Delhi Technological University | 2024 |
| 7 | Design and Analysis of Tow Thomas Biquad Filter | Prajwal Singh | Netaji Subhas University Of Technology | 2024 |
| 6 | Simulation and Frequency Response Analysis of a Wien Bridge Oscillator using eSim | Divyam Goyal | Punjab Engineering College (deemed To Be University), Chandigarh | 2024 |
| 5 | Chaos Circuit | Vivek Kumar | Shri Mata Vaishno Devi University | 2024 |
| 4 | Simple Up/down Fading Led Circuit Using 555 timer ic | Bipin Kumar | Shri Mata Vaishno Devi University | 2024 |
| 3 | Design and Simulation of frequency divider circuit | Arun Pandiyan P B | Karpagam College Of Engineering | 2024 |
| 2 | Optimal design of Twin-T notch filter using eSim | Nameera Jabi | Jamia Millia Islamia | 2024 |
| 1 | A 180 nm Low-Cost Operational Amplifier for IoT Applications | Krishan Kumar | National Institute Of Technology, Agartala | 2024 |