Guidelines :

1. Submit the completed circuit simulation files in a zip folder. You should compress the folder in zip format as it is, DO NOT RENAME THE PROJECTS. The folder should contain the following:
   
   • analysis
   • .bak
   • .cir
   • .cir.out
   • .pro
   • .sch
   • .sub(if subckt is used)
   • cache.bak
   • .lib.xml
     NOTE: Those working on mixed signal simulation projects(NGHDL or NgVeri) also need to submit the VHDL/Verilog files in the above zip folder.
2. Nomenclature related guidelines:
   1. Avoid spaces in eSim project name.
   2. There should be no special charachters in project name such as ( ) { } % # @ $ etc.
3. You also should submit an abstract in pdf format. The abstract should have the following (Mandatory):
   
   • Title
   • Theory/ description
   • Circuit diagram(s)
   • Results/ Output (ngspice and Python plots)
   • References
4. Project name should be meaningful and relevant to the circuit proposed.
5. Give the appropriate names and values to each circuit elements.
6. Give the label to respective nodes to plot input and output waveform.
7. Please see the sample of abstract here.
8. Please see the sample of project files here.
9. Use proper device models and subcircuits.
10. If you are unable to find the desired device models or subcircuits in eSim, contact us at: contact-esim (at) fossee (dot) in.
11. Once you have completed the project, then upload them through the interface only. ** Do not send it through email**.