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About the research migration
  • Proposer Name: Mr Dhruv Ojha
  • Title of the research migration: Design and Simulation of a Tunable Low-Power CMOS Delay Line Using Current-Straved Inverter Cells in eSim.
  • Source of the Project: Tunable CMOS Delay Gate With Improved Matching Properties Przemysław Mroszczyk, Student Member, IEEE, and Piotr Dudek, Senior Member, IEEE
  • University: Vellore Institute of Technology ,Bhopal