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About the research migration
  • Proposer Name: Ms Bala Sampurna Yerigala
  • Title of the research migration: Simulation and Transient Analysis of a 60-Gb/s 1:4 Demultiplexer in 22-nm CMOS Using TSPC Logic
  • Source of the Project: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 34, No. 2, February 2026, DOI: 10.1109/TVLSI.2025.3625787
  • University: Rajiv Gandhi University of Knowledge Technologies nuzvid
  • Name of the faculty: Dr sivalal kethavath