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About the research migration
  • Proposer Name: Mr Vishnu Vardhan Reddy Yerramala
  • Title of the research migration: Design and Simulation of Parallel CRC Using Pipelining, Unfolding and Retiming
  • Source of the Project: VLSI Implementation of Parallel CRC Using Pipelining, Unfolding and Retiming Author : Sangeeta Singh, S. Sujana, I. Babu, K. Latha https://www.researchgate.net/publication/271250418_VLSI_Implementation_of_Parallel_CRC_Using_Pipelining_Unfolding_and_Retiming
  • University: Rajiv Gandhi University of Knowledge Technologies