About the research migration
- Proposer Name: Ms Apoorva Singh
- Title of the research migration: Design and Simulation of an Efficient 1-bit Low Power Full Adder using GDI Technique
- Source of the Project: Title: Efficient Design of 1-bit Low Power Full Adder using GDI Technique
Author: Deepika Shukla, S.R.P Sinha
Page No.: 2073–2080 (Volume 6, Issue 7)
Link: https://www.ijsr.net/getabstract.php?paperid=ART20175733
Haseeb Pasha and Sangeeta Mangesh, "Study on various GDI Techniques for Low Power, High Speed Full Adder Design," JSS-ATE Noida Research Archive.
Link: https://www.semanticscholar.org/paper/Study-on-various-GDI-Techniques-for-Low-Power-%2C-Pasha-Mangesh/ab91faae08921d0514e77b364a48a1d60d85ac4d
Pankaj Kumar and Poonam Yadav, "Design and Analysis of GDI Based Full Adder Circuit for Low Power Applications," International Journal of Engineering Research and Applications (IJERA), Vol. 4, Issue 3.
Link: https://www.ijera.com/papers/Vol4_issue3/Version%201/CE4301462465.pdf
Shaik Salma and D. Vajida Parveen, "Implementation of Low Power Adder using GDI based Hybrid Full Adder," International Journal of Advanced Research in Science and Technology (IJARST).
Link: https://vlsijournal.com/index.php/vlsi/article/download/5/2
A. Morgenshtein, A. Fish, and I. A. Wagner, "Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits," IEEE Transactions on VLSI Systems. (Foundational Theory for GDI).
Link: https://ieeexplore.ieee.org/document/1039863
B. Revathi and K. Swaroop, "Design and Analysis of Low Power High Speed Full Adder Cell using Modified GDI Technique," ResearchGate/Google Scholar.
Link: https://scholar.google.com/scholar?q=Design+and+Analysis+of+Low+Power+High+Speed+Full+Adder+Cell+using+Modified+GDI+Technique+Revathi
- University: Vellore Institute of Technology
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