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About the research migration
  • Proposer Name: Ms Ramaprakash B
  • Title of the research migration: Design of a Fine-Grained Clock-Gated 4-Bit Counter for Low-Power Digital Systems
  • Source of the Project: This project is derived from published research on low-power VLSI design, with emphasis on latch-based glitch-free clock gating techniques. Traditional synchronous counters experience excessive dynamic power dissipation due to continuous clock activity. By studying prior work on clock gating and power-aware sequential circuits, this project applies those concepts to develop a fine-grained clock-gated counter for improved energy efficiency.
  • University: Anna University
  • Name of the faculty: Dr. R. M. Bommi