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About the research migration
  • Proposer Name: Mr Thejesh Varma Vulchu
  • Title of the research migration: Glitch-Free Clock Gating Circuit using Dual Muller C-Elements
  • Source of the Project: A Design of a Fast and Area Efficient Multi-Input Muller C-element - https://www.researchgate.net/publication/3336666_A_Design_of_a_Fast_and_Area_Efficient_Multi-Input_Muller_C-element Patent EP2515197A1: "Clock gating circuit using a Muller C-element," STMicroelectronics - https://patents.google.com/patent/EP2515197A1/en
  • University: Rajiv Gandhi University of Knowledge Technologies , Nuzvid