Completed Circuits

FOSSEE Project in collaboration with VLSI System Design (VSD) Corp. Pvt. Ltd and the Ministry of Education, Govt. of India conducted a 2-weeks high intensity eSim Circuit Design and Simulation Marathon using Skywater 130nm technology, a fully open source process design kit. Close to 3000+ students from all over India participated in this Marathon and close to 200+ students completed this marathon with brilliant circuit design ideas. The following participants have successfully completed designing the circuits. More details about this event can be found here: https://hackathon.fossee.in/esim/2021.

---

No	Circuit Name	Participant Name	Institute
138	Design and Analysis of a 2-input NAND Gate in 130 nm CMOS Technology	Soham Sen	Amity University Kolkata
137	CMOS Used As NAND Application	Hrishikesh Badiger	KLE Technological University
136	THREE PHASE INVERTER	Mohamed Abdullah	St. Xavier’s Catholic College of Engineering
135	CMOS NAND GATE	Cornilious v.g	St.Xaviers Catholic College of Engineering
134	Conversion of JK flip-flop to D flip-flop using CMOS-NOT Gate.	Sidhant priyadarshi	KLE Technological University
133	Low power and High speed 1 bit full adder circuit	Ayush Bhardwaj	KIET Group of Institutions Ghaziabad
132	CMOS Schmitt Trigger	Kalaiarul S	PSG college of technology
131	A Conventional 2 input CMOS NAND gate circuit	Vineet Gahlan	Dronacharya College of Engineering
130	NAND Gate Design	Sumanto Kar	FR. CONCEICAO RODRIGUES COLLEGE OF ENGG.
129	D Flip Flop	A.Saniya	KLE TECHNOLOGICAL UNIVERSITY
128	DESIGN AND ANALYSIS OF 2 INPUT NAND GATE USING 180nm CMOS TECHNOLOGY	Jittin Varghese Mathew	ASSSAM DON BOSCO UNIVERSITY
127	CMOS NAND Gate Circuit	Bhavana khanapur	KLE Technological University-Hubballi
126	two stage operational amplifier	n devi shivani	Anurag university
125	Implementation of a 8-bit CMOS Wallace Tree Multiplier	Karthik M B	Maven Silicon VLSI Training Center
124	Low Voltage CMOS Schmitt Trigger	SIBANI SASMALA	Maharaja Surajmal Institute Of Technology
123	Two Input NOR gate using CMOS	Yogeshwary Shinde	D.Y Patil Institute of Technology , Pimpri
122	Design of 2 bit Parity Generator using Pseudo NMOS logic	Mahisha.B.M	R.M.K.Engineering College
121	A Low Power 7T SRAM cell using Supply Feedback Technique CMOS	Vivek Arya	IIIT Allahabad
120	Design of 1-bit full adder using CMOS mirror logic	Bhawarth Gupta	Bharati Vidyapeeth College of Engineering Pune
119	Dynamic charge sharing comparator	Anmol Saxena	Dhirubhai Ambani Institute of Information and Communication Technology
118	1-bit NP-CMOS Dynamic Full Adder	John Johnson V	National Institute of Technology Calicut
117	double edge pulse triggered JK flip flop	S SHIVA SHANKAR REDDY	AMRITA VISHWA VIDYAPEETHAM
116	FULL ADDER USING CMOS	Dilip D	VELALAR COLLEGE OF ENGINEERING AND TECHNOLOGY
115	Portable Mobile Charger for outdoor trips	Aishik Das	University of Calcutta.
114	Positive Edge triggered D Flip Flop using Clocked MOS logic (Dynamic)	Tarush Singh	MCT rajiv gandhi institute of technology
113	Design of 4:1 Multiplexer using Transmission gates	Jyoti Balappa Halkarni	KLE Technological University
112	NMOS Schmitt trigger SRAM	Yash Bettgeri	Veermata Jijabai technological Institute
111	3_Stage_CMOS_Ring_Oscillator	Vikhas V	Sri Sivasubramaniya Nadar College of Engineering
110	NMOS Wilson Current Mirror	Nalinkumar S	Madras Institute of Technology Campus, Anna University
109	D Flip-Flop using CMOS	Jacintha Beena Mathias	Mangalore Institute Of Technology And Engineering
108	4-bit Carry Lookahead Adder	Aman Verma	University of Allahabad
107	Schmitt Trigger	DILIP BOIDYA	Tezpur University
106	Cmos XNOR gate	Adarsh S Shetty	Mangalore Institute of Technology and Engineering
105	CMOS Transmission Gate	Minautee	MIT World Peace University
104	Design and Analysis of two input NAND gate	MANJUNATHA	yenepoya institute of technology
103	8x4 right Barrel Shifter using NMOS pass transistor logic	Inderjit Singh Dhanjal	K. J SOMAIYA COLLEGE OF ENGINEERING
102	Two Stage CMOS Operational Amplifier	R.V.Rohinth Ram	Madras Institute of Technology Campus, Anna University
101	BGR using cascode current mirror	Priyanka L Patil	KLE Technological University Hubballi (India)
100	Design and Analysis of DIBO Differential Amplifier	Aditya Kalyani	Indian Institute of Technology, Dharwad
99	3T DRAM Cell	Aastha Dave	Birla Institute of Technology and Science Pilani, Hyderabad
98	Phase Frequency Detector for Phase locked loops	G Victor Swaroop	VNR Vignan Jyothi Institute of Engineering and Technology
97	3-bit resistor string DAC	T AKSHAYA	BITS Pilani Hyderabad Campus
96	Single Stage Operational Amplifier Using CMOS	Rithwik Jangam	Graphic era (Deemed to be University)
95	Low Power SRAM Cell	Vignesh Bharadwaj	BITS Pilani Hyderabad Campus
94	Half Adder	Shraddha Jayant Teli	KLE Technological University
93	Bandgap Voltage reference using OP-AMP architecture.	Vineet P N	KLE Technological University, Hubballi
92	Design of a Current Mirror Circuit in 130 nm CMOS Technology	Soham Sen	Amity University Kolkata
91	CMOS Design of 2:1 Multiplexer Using Complementary Pass Transistor log	Preetam Kumar	IIT Delhi
90	D FLIP FLOP USING TRANSMISSION GATES	DHATRISH TEWARI	NIT JALANDHAR
89	CMOS Differential cascade voltage switch logic(DCVSL) XOR-XNOR	Krishnamoorthy R	SRM Easwari engineering college
88	Operational Amplifier	Rohini Nandkumar Mhatre	Don Bosco Institute Of Technology
87	Design and Analysis of Two Stage CMOS Operational Amplifier	Abhishek Singh Kushwaha	Indian Institute of Information Technology, Dharwad
86	Design and Analysis of SR Flipflop	Chinmaya Nilakantha Naik	Mangalore Institute of technology and Engineering
85	Five -Stage CMOS Ring Oscillator	HIMANSHU BHATT	Mangalore Institute of Technology and Engineering
84	8 bit Successive-approximation-register Analog-to-Digital Converter	K Navaneeth	N.M.A.M Institute of Technology, Nitte
83	Low Noise Low Power Amplifier for Biomedical Applications	Mohammad Shama Parveen	Vignan's Institute for Science, Technology and Research
82	CMOS NOR Gate using SKYwater 130nm technology	ABU MAHAMED ADIL	ASSAM DON BOSCO UNIVERSITY
81	Design and Analysis of Two Input NOR Gate	Abhishek Bhat	Mangalore Institute of Technology and Engineering, Moodabidre
80	Design and Analysis of Half Adder	Nikethan Poojary	Mangalore Institute of Technology and Engineering
79	2:1 MULTIPLEXER USING PASS TRANSISTOR LOGIC	SOUVIK CHATTERJEE	KALYANI GOVERNMENT ENGINEERING COLLEGE
78	CMOS AS AN INVERTER CIRCUIT	Sudeshna Pahari	INSTITUTE OF RADIOPHYSICS AND ELECTRONICS, UNIVERSITY OF CALCUTTA
77	TWO INPUT XOR GATE USING CMOS 130nm	FATIMA SHABIR ZEHGEER	government college of engineering and technology ganderbal kashmir
76	CMOS NAND GATE USING 130NM TECHNOLOGY	Ilka Shawl	Government College of Engineering and Technology, Ganderbal, Kashmir
75	Implementation of 3 Stage Ring Oscillator Using CMOS	Ratul Chakraborty	University of Calcutta
74	2:1 MUX USING CMOS LOGIC	MOHAMED TOUSIF	ATRIA INSTITUTE OF TECHNOLOGY
73	Design of CMOS Transmission Gate based 4:1 MUX using SKY130 PDK	Supriya Khatoniar	Tezpur University
72	Transmission Gate Based Full Adder	Raghav Verma	Dronacharya Group of Institutions
71	CMOS NOR Gate	Amulya Narkhede	Ramrao Adik Institute of Technology
70	ONE BIT MIRROR ADDER WITH SKY130nm PDK & eSim tool	Shalini Kanna	University of Massachusetts Lowell
69	4 bit Binary to gray code converter using 2x1 MUX	Komal M Madikar	KLE Technological University
68	SRAM cell using TRIMODE MTCMOS power and ground gated technique	Ganesamoorthy B	Chegg India Pvt Ltd
67	MIRROR WITH MULTIPLE OUTPUTS	Kiran K Mudhol	KLETECH UNIVERSITY HUBLI
66	Design of Low Transconductance OTA	Mulpuri Divya	Vignans Institute for Science Technology and Research
65	DESIGNING AND IMPLEMENTATION OF SR FLIP-FLOP USING SKY130 Technology	Joji Jose	Government Engineering College, Idukki
64	4-Bit Parity Generator	S Sai Venkata Kishan Kumar	IIIT, Tiruchirappalli
63	RING OSCILLATOR	Tattukolla Gowthami	Vignan's Foundation for Science, Technology & Research
62	DESIGN OF 2-4 DECODER IN DIFFERENT CMOS LOGIC STYLES.	Pallepogu Divya	Vignan's Foundation for Science, Technology & Research.
61	NOR Gate - CMOS Technology.	Angelyn Sweety.I	St.Joseph's College of Engineering, OMR, Chennai.
60	2-INPUT CMOS NAND GATE	Harish krishna R	PSG College of Technology
59	Design of Exclusive-OR Gate using CMOS and SKY130 PDK technology	Mohammad Khalique Khan	Aliah University, Kolkata
58	4 Bit Binary to Gray code converter using Transmission Gate	Gyanvi Agarwal	Maharaja Surajmal Institue of Technology
57	Audio Power Amplifier	UPPALA BHARGAVA SAI	VNR VIGNANA JYOTHI INSTITUTE OF ENGINEERING AND TECHNOLOGY
56	Low power NAND gate based full subtractor using CMOS Technology	AAKASH.M	Easwari Engineering College
55	2:1 multiplexer using CMOS 130nm technology	SAYEEDURRAHMAN	ZHCET, Aligarh Muslim University
54	Analysis of CMOS Inverter	RAUNAK GIRI	Assam Engineering College
53	Multiplexer based design of Half Adder	Bindu Vaishnavi	VNR VJIET
52	NMOS Differential Amplifier	Ajay Kumar Sahu	NIT Jamshedpur
51	Symmetric CMOS NOR Gate	Sruthi Priya D.M	Easwari Engineering college
50	A D-Type Flip-Flop with Enhanced Timing Using Low Supply voltage.	Kesanasetty Leela Sravani	Vignan's Foundation for Science Technology and Research
49	Approximate compressors	Avula Swapnamadhuri	Vignans Foundation for Science Technology and Research
48	Design of 12 bit Carry Select Adder using CMOS Logic	Soorya Krishna K	Srinivas Institute of Technology, Mangalore
47	D Flip Flop using CMOS Technology	Gokul M	Atria Institute of Technology
46	Manchester encoder and Miller Encoder	Perumalla Durga Vasavi	Vignan's Foundation for Science Technology and Research
45	8T FULL ADDER	Vani chervirala	VNR VJIET
44	Folded Cascode Amplifier	Vesapaga Grace nissi	Vignan's Foundation for Science, Technology & Research
43	LowVoltageLowPower Amplifier based on MOSFET Darlington Configuration	MANGALAPALLY NAVEEN KUMAR	VNR Vignana Jyothi Institute of Engineering &Technology
42	Logic NAND gate design using Cmos	SUJATA HULLOLI	KLE technological University Hubli
41	Design of IC 741 tester circuit	TVN Srikar	VNRVJIET
40	2:1 Multiplexer using Transmission Gate	Raja Bisht	Birla Vishvakarma Mahavidyalaya
39	Design of Half Adder using CMOS Technology	Rutuja Kage	KLE Technological University,Hubli
38	Design of Approximate compressors	ketha chandana tejaswini	Vignans Foundation for Science and Technology and Research
37	Design and Analysis of Dickson Charge Pump using CMOS technology	Charaan S	Madras Institute of Technology Campus Anna University
36	Low Power CMOS Analog Multiplier using skywater 130nm pdk	Chiranjeevi R	PSG College of Technology
35	Darlington amplifier	Yogapriya B	Easwari Engineering College
34	2:4 Decoder using mixed logic CMOS gates	Akash Barman	Assam Engineering College
33	Implementation of Full Adder using SkyWater 130nm PDK	Balla Lalith Kumar	Gayatri Vidya Parishad college for Degree and PG Courses
32	CMOS 2:1 MUX Design and Implementation	A DEVIPRIYA	Cambridge Institute of Technology, K R Puram, Bangalore
31	DESIGN OF 3 INPUT NAND GATE USING CMOS	Ds Sai Rohith	SJCE MYSURU
30	The Two Stage CMOS Operational Amplifier with Frequency Compensation	Madhuri Hemant Kadam	Shree L. R. Tiwari College of Engineering
29	Designing and Plotting the characteristics of a Cascode Current Mirror	Archika Malhotra	INDIRA GANDHI DELHI TECHNICAL UNIVERSITY FOR WOMEN
28	Designing and Plotting the characteristics of a Cascode Current Mirror	Archika Malhotra	INDIRA GANDHI DELHI TECHNICAL UNIVERSITY FOR WOMEN
27	Transmission Gate	Vatsal B Patel	Vishwakarma Government Engineering College
26	CMOS Inverter	Vignesh	St Joseph Engineering College, Mangalore
25	Design and Analysis of TSPC D flip-flop using eSim	Aditi Singh	Indira Gandhi Delhi Technical University for Women
24	NOR gate using CMOS 130 technology	E BALAKRISHNA	DRONACHARYA GROUP OF INSTITUTION, GREATER NOIDA
23	Full wave Bridge rectifier using CMOS	Siddharth Hande	Dr. D. Y. Patil Institute of Technology
22	CMOS Rail-to-Rail Operational Amplifier	Manasi Yadav	Institute of Technology, Nirma University
21	NAND Gate using CMOS in 130nm technology performed in e-sim	Vanshika Tanwar	Dronacharya Group Of Institutions
20	RC Phase Shift Oscillator using FET	Samyuktha Shrruthi K R	Easwari Engineering College
19	Ring Oscillator Using Sky130	ROHAN V PATIL	KLE TECHNOLOGICAL UNIVERSITY
18	Miller compensated Two stage operational amplifier	Anjana Jahagirdar	KLE Technological University,Hubballi,Karnataka
17	Design of two stage op-amp	Mili Anand	IGDTUW
16	Current mode logic CML latch	Abhishek Bhandari	IIT Dharwad
15	CMOS 3 STAGE RING OSCILLATOR using 0.25u CMOS TECHNOLOGY	AAKASH K	CAMBRIDGE INSTITUTE OF TECHNOLOGY ,K R PURAM BENGALURU
14	High Efficiency Dc-Dc Buck Boost Converter	ADITYA WAGH	Walchand College of Engineering, Sangli
13	Gilbert Multiplier Cell	Vaikunth Guruswamy	Madras Institute of Technology, Anna University
12	2x1mux using CMOS	Barnali Mukherjee	Kalyani Government Engineering College
11	32-bit ALU	PARAS SANJAY GIDD	Manipal Institute of Technology
10	Voltage Divider	Jayantha Nayak	Mangalore Institute of Technology and Engineering, Moodubidri
9	SR Flip Flop using CMOS Technology	Manjit Kalita	Assan Engineering College
8	CMOS Inverter	Dinesh Babu P	Sri Ramakrishna Engineering College
7	3T NAND gate	Akhil Hadli	BMS College of Engineering
6	Full Adder using CMOS	Prerana Das	Assam Engineering College
5	Full Adder implementation on Dynamic CMOS Logic	Shreyas Bhat	KLE Technological university
4	CMOS SCHMITT TRIGGER	Vighneshwar B Hegde	KLE Technological University Hubballi
3	2:1 Multiplexer using CMOS logic	Jessica Danica Vaz	Nitte Meenakshi Institute Of Technology
2	D Latch using CMOS Transmission Gate(TG) switches	Ankit Borah	Assam Engineering College
1	AND gate using CMOS technology	B ABHISHEK	KLE technological university, HUBLI