Download Codes

About the research migration
  • Proposer Name: Mr Chongali Aravind
  • Title of the research migration: Implement 32-bit RISC-V Architecture Processor using Verilog HDL
  • Source of the Project: DESIGN OF 32 BIT RISC V PROCESSOR,https://ieeexplore.ieee.org/document/10726132
  • University: Rajiv gandhi university of knowledge technologies , nuzvid