Project: Design and Simulation of an 8-bit DPCM Encoder Circuit
Participant: Meghna Pradeep
Affiliation: Department of Electronics and Communication Engineering, MITS

Simulation Instructions:
1. Open eSim 2.5 and load the project 'DPCM_8bit_Encoder'.
2. Run the simulation directly by clicking the 'Simulation' button (do not re-run 'KiCad to Ngspice' to preserve explicit XSPICE ADC/DAC mixed-signal bridge models).

Visualization in eSim Python Plotter:
In the Python Plotting tab, select:
  - Clock: net-_u25-pad1_
  - Difference Bit 1: v_d1
  - Borrow-Out: v_bout
Click 'Plot' to observe discrete logic switching for +2 and -1 (borrow) transitions.

Visualization in Ngspice Console (Multi-bit Bus Waveforms):
At the open 'ngspice ->' prompt, run the following commands:

A. Vertically Stacked Input Bus:
   let in0 = v("net-_u17-pad1_")
   let in1 = v("net-_u18-pad1_") + 10
   let in2 = v("net-_u19-pad1_") + 20
   let in3 = v("net-_u20-pad1_") + 30
   let in4 = v("net-_u21-pad1_") + 40
   let in5 = v("net-_u22-pad1_") + 50
   let in6 = v("net-_u23-pad1_") + 60
   let in7 = v("net-_u24-pad1_") + 70
   let clk_in = v("net-_u25-pad1_") + 80
   plot in0 in1 in2 in3 in4 in5 in6 in7 clk_in

B. Vertically Stacked Complete 8-bit Output Bus:
   let d0 = v(v_d0)
   let d1 = v(v_d1) + 10
   let d2 = v(v_d2) + 20
   let d3 = v(v_d3) + 30
   let d4 = v(v_d4) + 40
   let d5 = v(v_d5) + 50
   let d6 = v(v_d6) + 60
   let d7 = v(v_d7) + 70
   let bout = v(v_bout) + 80
   let clk_out = v("net-_u25-pad1_") + 90
   plot d0 d1 d2 d3 d4 d5 d6 d7 bout clk_out

C. Reconstructed Decimal Bus Waveform:
   let v_diff = (v(v_d0)/5)*1 + (v(v_d1)/5)*2 + (v(v_d2)/5)*4 + (v(v_d3)/5)*8 + (v(v_d4)/5)*16 + (v(v_d5)/5)*32 + (v(v_d6)/5)*64 + (v(v_d7)/5)*128
   let v_bout_scaled = (v(v_bout)/5)*250
   let clk_scaled = (v("net-_u25-pad1_")/5)*50
   plot v_diff v_bout_scaled clk_scaled