Previously I have submitted the initial report for "Pipelined ADC" but because of unavailability of proper Opamp IP I decided to change my project after discussing with Kunal Sir. And after Kunal Sir's approval i changed my project to "4-bit Pipelined Vedic Multiplier using KSA" and here i am submitting all the files and reports for multiplier project.

Folder Description:
1. Final Report:
	Contains the Final report for "4-bit Pipelined Vedic Multiplier using KSA".

2. Literature Survey
	Contains the Initial survey report after the project change.

3. vedic_multi_4bit_test
	Contains the project file for the combinational design of the Multiplier.

4. vedic_multi_4bit_pipelined_test
	Contains the project file for the pipelined design of the Multiplier.

5. Verilog_Codes
	All the verilog code used and transactional verilog code generated is present in this folder.