
8x4 right Barrel Shifter using NMOS pass transistor logic

Execution of tasks: 
1. Circuit schematic in eSim 
a) To build 8x4 right barrel shifter using only NMOS transistors, a total of 20 transistors, 8 input bits from In0 to In7, 5 control shift bits from S0 to S4 and 4 outputs bits from Out0 to Out3 were required. 
b) The gate terminal of each NMOS transistor in a column is connected to one control shift signal as input. At a time only one control signals (from S0-S4) are enabled high while others are low.
c) To start with, an 8x4 wire grid was made, and subsequently 5 transistors were added in a row, In this way, all four rows were complete. The necessary control signals for simulation purposes were considered as follows: 
S0 = 0, S1 = 0, S2 = 0, S3 = 0 and S4 = Vdd 
d) Next, 12 ports were added to the inputs and outputs sequentially
e) Next, label was carried out for wires connecting the port, 8 inputs were labeled as Input_In0 to Input_In7 and 4 outputs were labeled as Out0 to Out3
f) Next task was to rename all the ports by editing the reference field (Pressing e near the port name) one by one. The ports were named as U1A, U2B to U12L
g) Next task was to rename all the NMOS transistors by editing the Field Value (in component properties) one by one. The transistors were names as M1, M2 to M20 
h) Next, electric rules check was executed, upon which it showed one error, which was overcome by placing PWR_FLAG at ground node. Again electric rules check was executed, this time it showed zero errors. 
i) Next task to perform was of generating netlist. To do this, click on generate netlist, in options select Spice, tick the default format, and then click on the Generate button. The Netlist for barrel shifter was saved in ESim workspace with default Netlist Filename as barrel_shifter.cir

2. Adding sky130 pdk 
a) Once the netlist was generated in eSim Workspace, the next task was to add sky130 pdk in the same folder as barrel_shifter.cir file. 
b) The following steps were carried out to download and add sky130 pdk
Download sky130 from this link and unzip :
 https://github.com/google/skywater-pdk-libs-sky130_fd_pr
Step1. Save the cir.out file in the sky_fd_pr folder as .cir file.
Step2. Open with notepad and add the path .lib "sky130_fd_pr/models/sky130.lib.spice" tt at the top.
Step3. Replace with mosfet_n with sky130_fd_pr__nfet_01v8 

3. Editing the NETLIST 
a) To execute the .cir file, follow these steps:
Step 1: Open the .cir file (barrel_shifter.cir in my case) with notepad 
Step 2: Make sure the path .lib "sky130_fd_pr/models/sky130.lib.spice" tt at the top.
Step 3: Make sure that all mosfets are replace with sky130_fd_pr__nfet_01v8
Step 4: Delete any / added if any 
Step 5: Prefix x with all Transistors starting with M. Do this for all transistors 
e.g Before M1, after xM1
Step 6: Comment with * if any ports are added by defaults 
e.g *U1  /Input_In0 PORT	
*U9  /Out0 PORT	
Step 7: Next Start adding Inputs sources, supply voltage, etc (Vdd was considered as 1.8V)
Step 8: Add .tran statement with initial step time and final stop time 
eg. .tran 0.4ns 40ns 
Step8: Add .control command and run command to run the plot 
Step9: Add the voltage or current input or output quantities to be plotted 
eg. plot V(Input_In0) 
plot V(Out0) 
Step 10: Last step is to add .endc followed by .end command 

4. Executing in ngspice 
a) After all the editings in NETLIST, right click on .cir file and open it with ngspice 
b) It will take around 10 to 15 seconds, before it open ups al the plots with black background. 
c) I did encountered with an error while executing .cir file for the first, It so happened that removing L and W from sky 130 model statement, solved this problem after 2nd rerun
d) All the 8 inputs and 4 outputs plots were successfully opening. That completes ngspice execution step

5. Timing specifications: 
a) In barrel shifter circuit, a total of 8 inputs from In0 to In7 were given as pulse signals.
b) All pulse inputs have same high voltage level of 1.8V, and had same on time of 10ns and stop time of 20ns
c) All pulses were differing from each other w.r.t delay time.
In0 was given 4ns as delay time, and In7 was given 9nsec as delay time 
d) This made sure that, none of the inputs were overlapping. 
e) Transient time step size was taken as 0.04ns with stop time as 40ns 

Pulse definitions for 8 inputs in NETLIST
V1 Input_In4 0 PULSE(0 1.8 1n 10p 10p 10n 20n)
V2 Input_In6 0 PULSE(0 1.8 7n 10p 10p 10n 20n)
V3 Input_In5 0 PULSE(0 1.8 3n 10p 10p 10n 20n)
V4 Input_In7 0 PULSE(0 1.8 9n 10p 10p 10n 20n)
V6 Input_In0 0 PULSE(0 1.8 4n 10p 10p 10n 20n)
V7 Input_In1 0 PULSE(0 1.8 8n 10p 10p 10n 20n)
V8 Input_In2 0 PULSE(0 1.8 12n 10p 10p 10n 20n)
V9 Input_In3 0 PULSE(0 1.8 16n 10p 10p 10n 20n)

6. Making sense of the output ( Right Barrel Shifter circuit) 
a) For simulation purpose, the control bit S4 is enabled (tied to Vdd), the inputs bits are shifted right by 4 bit position and the output bits are at Out0 = In4, Out1 = In5, Out2 = In6, Out3 = In7. 
b) From the NgSpice output plots, the output shifted bits are cross-validated/confirm the functionality of the circuit. 

6. Limitation of circuit: 
a) The output bits suffer from threshold voltage (VTn) drop i.e maximum output voltage level is limited to VDD - VTn which can be overcome by using transmission gates instead of pass transistors. In our case, Vout was near to 1.2V peak.
b) Glitches were observed, whenever output state made a high to low transition. Glitch duration was less 0.2ns and it overshoots to 2.4V momentarily before reaching logic 0 level. 


FINAL BARREL SHIFTER SPICE NETLIST LOOKED LIKE THIS: 

* C:\Users\etr\eSim-Workspace\barrel_shifter\barrel_shifter.cir

* EESchema Netlist Version 1.1 (Spice format) creation date: 6/29/2021 11:56:39 PM

.lib "sky130_fd_pr/models/sky130.lib.spice" tt

* Sheet Name: /
xM2 Out0 GND Input_In1 GND sky130_fd_pr__nfet_01v8 		
xM1 Out0 GND Input_In0 GND sky130_fd_pr__nfet_01v8 		
xM4 Out0 GND Input_In3 GND sky130_fd_pr__nfet_01v8 		
xM3 Out0 GND Input_In2 GND sky130_fd_pr__nfet_01v8 		
xM5 Out0 Vdd Input_In4 GND sky130_fd_pr__nfet_01v8 		
xM7 Out1 GND Input_In2 GND sky130_fd_pr__nfet_01v8 		
xM6 Out1 GND Input_In1 GND sky130_fd_pr__nfet_01v8 	
xM9 Out1 GND Input_In4 GND sky130_fd_pr__nfet_01v8 		
xM8 Out1 GND Input_In3 GND sky130_fd_pr__nfet_01v8 		
xM10 Out1 Vdd Input_In5 GND sky130_fd_pr__nfet_01v8 		
xM12 Out2 GND Input_In3 GND sky130_fd_pr__nfet_01v8 		
xM11 Out2 GND Input_In2 GND sky130_fd_pr__nfet_01v8 		
xM14 Out2 GND Input_In5 GND sky130_fd_pr__nfet_01v8 	
xM13 Out2 GND Input_In4 GND sky130_fd_pr__nfet_01v8 		
xM15 Out2 Vdd Input_In6 GND sky130_fd_pr__nfet_01v8 		
xM17 Out3 GND Input_In4 GND sky130_fd_pr__nfet_01v8 	
xM16 Out3 GND Input_In3 GND sky130_fd_pr__nfet_01v8 		
xM19 Out3 GND Input_In6 GND sky130_fd_pr__nfet_01v8 		
xM18 Out3 GND Input_In5 GND sky130_fd_pr__nfet_01v8 		
xM20 Out3 Vdd Input_In7 GND sky130_fd_pr__nfet_01v8 		
*U1  /Input_In0 PORT		
*U2  /Input_In1 PORT		
*U3  /Input_In2 PORT		
*U4  /Input_In3 PORT		
*U5  /Input_In4 PORT		
*U6  /Input_In5 PORT		
*U7  /Input_In6 PORT		
*U8  /Input_In7 PORT		
*U9  /Out0 PORT		
*U10  /Out1 PORT		
*U11  /Out2 PORT		
*U12  /Out3 PORT		
*U13  /Vdd PORT		

V1 Input_In4 0 PULSE(0 1.8 1n 10p 10p 10n 20n)
V2 Input_In6 0 PULSE(0 1.8 7n 10p 10p 10n 20n)
V3 Input_In5 0 PULSE(0 1.8 3n 10p 10p 10n 20n)
V4 Input_In7 0 PULSE(0 1.8 9n 10p 10p 10n 20n)
VDD Vdd 0 1.8V
V6 Input_In0 0 PULSE(0 1.8 4n 10p 10p 10n 20n)
V7 Input_In1 0 PULSE(0 1.8 8n 10p 10p 10n 20n)
V8 Input_In2 0 PULSE(0 1.8 12n 10p 10p 10n 20n)
V9 Input_In3 0 PULSE(0 1.8 16n 10p 10p 10n 20n)

.tran 0.4ns 40ns 

.control
run
plot V(Input_In0) 
plot V(Input_In1) 
plot V(Input_In2) 
plot V(Input_In3) 
plot V(Input_In4) 
plot V(Input_In5) 
plot V(Input_In6) 
plot V(Input_In7) 
plot V(Out0) 
plot V(Out1) 
plot V(Out2) 
plot V(Out3)  

.endc
.end