CMOS Transmission Gate

1. In this circuit, we used sky130 PMOS and NMOS by including the library path and gave control signal to NMOS and its complementary to PMOS.

2. Then we gave input to the circuit, connected between vin and ground in the pulse form by keeping delay 0-500ps, rise time as 500ps, width of signal as 20ns and period of 40ns.

3. Then we gave input to the Vc signal, connected between C and ground in the pulse form by keeping delay 0-500ps, rise time as 500ps, width of signal as 15ns and period of 30ns.

4. Similarly, we gave input to the Vcbar signal, connected between Cbar and ground in the pulse form (values opposite to C) by keeping delay 0-500ps, rise time as 500ps, width of signal as 15ns and period of 30ns.

5. The transient analysis is performed between 0ns to 100ns.

6. Finally control, run and plot commands were given for the output. 

7. The output observed complied with signals status i.e when C was high, a low resistance path was observed and current was allowed to pass and when C was low, a high impedance path was observed and the current was not allowed to pass. 

Problems Faced:
In the graph, when C was low, output is observed to higher in the first half. I couldn't figure out the reason. The rest of the graph is alright. 

The graph was even checked for sinusoidal input and the results were found to be correct. The input signals were allowed to pass for C=high and were not allowed in case of C=low.

