The circuit design and netlist generation are implemented by esim EDA tool and we use hierarchical sheet instead of subcircuit because we faced too many issues in subcircuit designing. In Hierarchical sheet many sheets are connected to each other in single file. There's no need to attach subcircuits but still we can design our large circuit by beaking in small blocks. After updating esim created netlist file by using SKYWater 130nm pdk library, evaluated outputs in ngspice tool of 4 bit CLA Adder circuit. We used power supply approx. 1.95v and for this the value of “w” and “l” is given in skywater130nm pdk document for both nmos(w=.42 l=.15) and pmos(w=.55 l=.15). 
There are 2 types of distortion coming in output waveform. One is overshooting at rising and falling edge of output which is solve by adding buffers in the output points. Second is glitches comes due to rising and falling edge delay of the input. It will not affect the output logic but in mid of the logic it's instantaneously logic drop or rise for a very short time(approx =0.5ns) then again back it's previous position. It is negligible.
In input ports we used pulse inputs with randomly different frequency for making different combination on the input ports. 