Design Staement:
Design of 4:1 Multiplexer using Transmission gates

A Brief Description of Proposed Design.
Low power consumption is one of the most critical concerns in system SOC design, and several methodologies and technologies for low-power designs in high-speed interface applications are being developed and tested in real-world projects. Various techniques to reducing MUX tree power usage have been presented.Multiplexers play a crucial role in CMOS memory and data manipulation systems. The growing demand for low-power very large scale integrated circuits (VLSI) can be addressed at several design levels, such as architectural, circuit, and layout.

Transmission logic gates are used in the proposed 4:1 mux architecture. In comparison to a standard CMOS-based design, this design is a transmission gate kind of MUX structure implemented with very few transistors. The 4:1 MUX has a transistor level architecture with 44 transistors. Only 12 transistors are used in the 4:1 MUX architecture based on transmission logic gates.As a result, the amount of energy used and the amount of space required are lowered.

The circuit is designed using eSim and simulated using ngspice simulation tool.
For my final design i have tried giving all the possible input combinations (4 bit data=16 combinations and 2 select lines= 4 combinations) and have sucessfully got the correct output. 
Note:Inputs for the are x0 ,x1, x2 and x3 and select lines c0 and c1.
(In the reference uploaded waveform Inputs are d0 d1 d2 d3 and select lines A and B).

Defination
Multiplexer
The design of large-scale digital systems, that a single line is required to carry two or more different digital signals.They are used as one method of reducing the
number of integrated circuit packages required by a particular circuit design. This in turn reduces the cost of the system.

Objectives.
1.As Mutiplexer is one of the important building blocks in ALU or DSP blocks or for other digital designs which are to be mapped onto the LUTS on fpga. As,LUT's can be designed using MUX.
2.Transmission logic gate based MUX mainly helps in reducing the power as low the power consumption is one of the impoartant key factor in the VLSI industry.
3.We can also observe that to design a 4:1 MUX using conventional CMOS logic gates ,the total number of transistors required are 44, where as in designing a 4:1 mux using transmission logic circuits only 12 transistors are required.
Thus,using the transmission Logic Gate based MUX deign in place of conventional CMOS logic gates based mux,we can achieve low power consumption and small area.


Conclusion
The NMOS and PMOS are coupled for a strong output level to remove poor output. The number of transistors is greatly reduced, resulting in a smaller overall area.

