Execution
Positive Edge triggered D Flip Flop using Clocked
MOS logic (Dynamic) This circuit has a great advantage
over the conventional CMOS or Pass Transistor.
We have used a Two-phase clock that is nonoverlapping
routing delay would not cause clock skew. The
implemented logic function or the logic gate is achieved
through 2 modes of operation: Precharge and Evaluate.
The number of transistors required here is less
(N+2) than 2N in the Static CMOS circuits. This circuit
is still a ratio-less circuit as in the case of Static.
The static power loss is very less in a dynamic logic circuit
and has a faster switching speed because of lower
load capacitance of 0.0001uf.In total 14 transistor is used
i have set internal complemented clock.


Problems
1)Difficulty to set capacitor value to get the appropriate graph
2)Difficulty to set pulse parameter to get appropriate graph
3)good amount of syntax error

Next Stage
I have taken my circuit to next stage with the devlopment of 
subcircuit i have also developed SISO register of D flip flop 
with same sky130 pdk and i am looking forward to develop it into a memory element
 