The schmitt_trigger is deviation in inverter with four additional mosfets compared to conventional inverter. 
The waveform shown in reference circuit was done using cadence tool with global foundry pdk. The noise or glitch in output waveform here is because of the absence of output capacitor. As the inverter output is fed to the successive logic stages the circuit gets output capacitance as the gate capacitance of next stages, hence glitches here can be ignored.

Design: Let us consider wi as size of ith mosfet.
w6/w2= (Vuh-Vthn)^2/(Vdd-Vuh)^2
w5/w3=(Vlh)^2/(Vdd-Vlh-|Vthp|)^2
Taking Vuh=1.2v , Vlh=0.6v and length of mosfet as 150nm,
we get w6=w5=1.7w3=1.7w2
Vuh :upper switching voltage
Vlh :lower switching voltage

The design is simulated with sinfunction input of amplitude 0.9v with dc bias 0.9v giving rise to peak to peak voltage of 1.8v. 

The waveform will not be clear as this if plotted separately as in reference waveform and it is hard to figure out the switching points. 

The challenges that persisted for longer time were finding a good literature for reference and running the netlist on ngspice tool.

