The Complete Process of learning, Designing and implementing the circuits through open source tool Esim and Ngspice along with the guidance of mentors was very informative, fun to do and knowledgable.
During the start as The research part was new to me i found it quite challenging. But through some effort and guidance it went all. After Selecting the circuit and completing the literature survey the next part of designing the circuit with esim was quite difficult at the start but as an when we got the DAC IP design course, All the issues were sorted 
My circuit was based on 1-bit Full adder design using dynamic CMOS logic. It used Cross coupled model (for XOR) and XNOR operation for implementing the circuit . During the design part of this i found it that due to delay in output to input in cascaded xor logic in Cross coupled model and some other implementing issues with Cross coupled model.
As it was inefficeint and had too many errors which esim could resolve, Mr.Sumanto suggested me to build and alternate logic circuit for cross coupled model.
Hence i changed my circuit to Full adder using CMOS logic which didnt have Cross coupled model.

Some of the errors i faced were as follows:

No such vector exists
Not getting simpulation output in ngspice
SKY130 mapping errors.

It was a Very knowledgable 2 Weeks marathon. I wish to participate in Future marathons and learn from it.  