-----------------------------------Part 1 - IDEA------------------------------------

I got intriguied by the idea of 32-bit ALU which i found on
http://www.csc.villanova.edu/~mdamian/Past/csc2400fa13/assign/ALU.html
(Please have a look)
the proposed design is quite simple & understandable in single read.


-----------------------------------Part 2 - HURDLES ------------------------------------

But, this hackathon wasn't just about designing but
as we have to follow certain rules
I first learned ESim by DAC Course,
integrating sky130 , modifying netlist & human error in possibly every single step in between made it harder than I anticipated.

-----------------------------------Part 3 - MODIFIED PLANS ------------------------------------

I had to breakdown my project till ONLY FULL ADDER & FULL SUBTRACTOR
(WHICH I PROMISED/PRESENTED IN 1ST REPORT as i was certain that even if i can't do whole 32-bit ALU, i will at least do part of it. )

-----------------------------------Part 4 - steps/work i did  -----------------------------------

1. logic understanding & implementation - in both FA & FS, sum & difference can be obtained by same circuitry as equations are identical.
but for carry & borrow, i have designed 2 different circuits.

2. currently in the submitted netlist file
there are 2 plot commands which will plot FA & FS individually

-----------------------------------Part 5- Future work  -----------------------------------
now we have FA, FA, bitwise AND & similarly can design bitwise OR
then these 4 lines will be connected to 4:1 mux which will create 1 bit ALU

& cascading such 32 blocks will create 32 bit ALU.

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