READ ME


///// About the waveforms /////

1. I have made a positive level triggered latch.
2. There are two plots I have attached, both waveforms are same only.
   the only difference is, in the first plot, waveforms are overlapping so, it may be difficult to see its latch behaviour.so that's why I have add/subtract 0.5 DC voltage, to make them more clearer.
3. output_n and output are just opposite to each other.
4. Time period of clock = 5n sec.


/////// how I design my circuit ///
CML latch has the two sub parts: CML buffer and regenerative latch. I have designed them separately and then combined it to get the latch.

1. CML buffer : The basic CML buffer is the simple differential amplifier with resistor loads. Let the VDD is the supply voltage, I is the tail current and vth is the threshold voltage of NMOS.

The transistors are in saturation, which is desirable.The transistor which is closest to getting into triode is the one whose input is at VDD. In
this case the transistor will be in saturation if
VGS - Vth < VDS
Vgate < Vdrain + Vth
VDD < VDD - IR + Vth
IR < Vth
minimum value of Vth for sky 130nm pdk at corner tt = 400m V
and let I = 1mA
so, R < 400m/ 1m
    R< 400  ohms
I have taken R= 250 ohms in my design.


The minimum input differential that results in complete switching of the output is when M2 is just off and all the current Io flows through M4(this can be treated as boundary condition).
VGS(M2)= vin_plus = Vth
VGS(M4)= vin_minus = Vth + sqrt(2I/µCoxW/L)
vin = vin_plus - vin_minus = sqrt(2I/µCoxW/L)
to make this act as amplifier, we want gain>1 => vout/vin >1
if we made gain>1 for boundary condition then obviously gain>1 for rest of the situations.
Vout for boundary condition = Vout_plus - Vout_minus =  IR
for gain>1
sqrt(2I/µCoxW/L)  <  IR

 I =  1m ampere (we have already assumed)
R = 250 ohm (already proved)
µCox we can approximate for sky 130nm technology. so from here I have taken the value of W/L for nmos M2 an M4, w= 40u and L = 0.18u


1. CML regenerative latch :
A regenerative latch in CML logic can be implemented by connecting the output to
the input in positive feedback as shown in circut.png
time evolution of the output voltage will be
v(t) = v(0) × exp(gm− 1/R)C
 where v(0) = initial volatge
	C = parasitic capacitance
	
so, gm value for M6 and M8 should be greater than 1/R.
R = 250 ohms
value of gm is depends on I, µCox and W/L values.
and I took W/L for nmos M6 an M8 same as M2 and M4. so, that Rout will be same for all4 transistor and when it comes to charging ans dischaging their time constant would be same.
W/L for nmos M6 an M8, w= 40u and L = 0.18u

Final CML latch: 
To complete the latch,we also need two extra mosfets M3 and M7 whcih will connect to the controlling plus (clock).
To get a +ve level latch, I have connect clock to differential amplifier and clock_bar to regenerative latch.
When clock is high, the second stage with positive feedback is disabled, and the circuit is a simple differential amplifier. This is the phase when the output tracks the input with some gain. When the clock goes low, the input amplifier stage is disabled, and the regenerative second stage is activated. The second stage then regenerates from where the amplification stage left the outputs and produces a logic output depending on the sign of the initial voltage.

In the end, I have made a current mirror using M1 and M5 transistor and we have to take W/L ratio of M5  =  W/L ratio of M1 to get same mirror current.
W for M5 and M1 = 50u
L for M5 and M1 = 0.18u
