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Two stage operational amplifier
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This netlist presents two stage operational amplifier and the topology of the circuit is that of standard CMOS op-amp. The specification for the circuit file was as follows :-
1) Gain= 1000, 
2) GBW = 30MHz 
3) Phase margin should be taken greater than 60 deg
4) Slew rate = 20V/m 
5) ICMR= 0.8 to 1.6 
6) Load capacitance = 2pF

The calculation result of NMOS/PMOS sizes  in the op-amp circuit are as follows:-
1) For M1/M2:- W/L= 5
2) For M3/M4:- W/L=4
3) For M5/M8:- W/L= 7
4) For M6:- W/L= 105.83
5) For M7:- W/L= 45.3
6) I5= 20uA, gm=160u
7) Minimum and maximum threshold voltages for M1 and M3 required for the calculations were taken from the sky130 website.
8) Kn was calculated by dc analysis of NMOS  and executing the "showmod all" command in ngspice to get different paramters values at dc operating voltage. Formula used for the calculation is :-
Kn=u0xCox  [u0--> 0.03138 (mod parameter), Cox- (tox,Eox)]= 260u
9) Kp was similarly calculated and its value is 80u.

Problem faced:-
1) Ideally, according to specs taken the open loop gain should be 60db but here if we observe the phase margin plot there is a pole at a very low frequency due to the gain plot does not match.
2) The transient analysis yields a more slanted sine wave though output voltage seems to be amplified.
3) Difficult to find the problem with the op-amp by only observing the circuit file.
4) Could not link the sky130 cap models.
 

