

Title: Two stage CMOS OPAMP with RC compensation simulation with eSim and Skywater 130nm Technology

1) Initially I completed the 2 bit DAC Course and simulated it in eSIm using skywater 130nm and got the waveforms as shown in video.
2) To get above waveforms I separetly installed ngspice v34. Extracted the netlist from eSim and run the .cir n .out file n Ngspice 34
3) I got the desired output of 2 bit DAC in ngspice v34. I tried to run the same file .cir . .out file in esim ngspice v30 but it was taking too long to simulate. so i stopped it.
4) It took 4 days to complete 2 bit DAC.
5) After that i started with my design of Two stage CMOS OPAMP. I divided the main circuit into two parts for simulation a) Opamp_bias b) Diff_amp with  RC compansation and 2nd stage CS amplifier.
6) I designed OPAMP bias circuit (Opamp_Bias) with 6 MOSFETs and 5v of supply voltage in eSim. Extracted the netlist from eSim and executed .cir file with .tran n plot command to view the output of Bias ckt.
7) In reference paper they have got 20uA reference current with 10k resistor. But i was getting it as 1.87 uA so i changed the resistor value to 1k n i got 18.7uA of reference current. 
8) By considering 18.7uA close to 20uA i noted down the voltages at Va Vb n Vc. I got Va as 3.9v which is the (Vbias) Bias voltage for Diff-amp and 2nd stage CS amlifier.
9) After that i started with design of Differential amplifier in eSim by creating a new project name Diff_amp.It includes the Rc compensation circuit and 2nd stage CS ampplifier as well.
10) Here i initially applied bias using vbias port n giving its value as 3.9 v in netlist.
11) In reference paper they had used 0.8um process so they were having W/L ratios of some of the MOSFETs as 220/1 700/1 and 3500/1. 
12) I simulated the circuit with same W/L ratios as per reference paper but it gave me error of "No compatibility n can not find model"
13) So I reduced the W/L of those transistors to 22/1 70/1 and 35/1 n simulated again.
14) This time i got the proper output i.e Magnitude frequency response (Vdb of Vout) with 62dB gain and unity gain Bw of 10MHz matching with reference paper.
15) But the Phase reponse nature is same as per reference paper but values are not matching with reference paper.
16) Afetr that i connected bias ckt to Differential amplifier in eSim by using sucircuit approach n simulated the same but there i got reduced output voltage.
17) This reduction in Vout is almost by 40dB i.e i m getting Vout around 22dB at lower frequency. I tried to recorrect it by changing W/L values of mosfets.
18) So i scaled down all Ws by 100. With this max W/L of one MOSFET was 35:1 and smallest w/l is 0.1:1. But with these ratios it was giving "No comapatibility error" 
19) So Diffamp circuit is giving proper 62dB Vout if not connected to bias circuit. If connected to bias ckt then there is reduction of 40 db in Vout. 
20) According to me this may be due to loading effect as Diff-amp ckt is acting as load to Bias-ckt. Or i have to rework on sizing of all MoS transistors to match the impedance between bias ckt n Diff-amp ckt.
21) But as there is a deadline it is not possible to redesign the whole ckt nw so i will be uploading the present project files as it is.
22) which includes 1)Combined file of Diff-amp with bias i.e. Diff_amp_combined.cir.out and Opamp_bias.sub file 2)Individual Opamp_bias.cir file for only bias ckt outputting va=3.9 V 3) Main Individual Diff_amp_Opamp.cir.out file with Vbias=3.9V 
23) .cir file includes transient as well as AC analysis. currently transient analysis with transient source has been commented out. So when any file is run it will perform AC analysis n we can see magintude and phase response.
24) To see the transient response please comment out the AC command with ac sources and then run the file to see the vinp, vipm and vout waveforms.
25) I have discussed all these isshues with Sumanto Sir n as per his directions i am uploading all these files.

Conclusion: Both Circuits i.e. Bias and Differential Amplifier are working fine if they are simulated individually. 
But the moment they are connected using subckt, Vout reduces drastically to 22dB also if we observe vbias at that moment it is no more 3.9 DC, insted it turns into sinusoid signal
hence there is distortion in vout. It may be due to loading effect.


