In this project we have made and simulated a low power 2:4 decoder using 14 CMOS transistors.Decoder is a
combinational circuit and is widely used in the periphery circuitry of memory arrays like Static RAM.
The circuit is designed using a mixed logic style which is a combination of Transmission Gate Logic (TGL)
and Dual Value Logic (DVL). The circuits that are designed using mixed logic exhibit better performance
and more compact when compared to the circuits designed using the static CMOS logic

The schematics is proposed in e-Sim and then the netlist is extracted and Ki-Cad to Ng spice conversion is done.
After that we have copied the cir.out file from the workspace to a new folder where the downloaded sky130_fd_pr
existed. The modified netlist is uploaded along with the literature review. Then we opened the modified netlist
through the ngspice