Designing steps to Implement 12 bit Adder using CLAA Logic.
1. Implemented 1 bit adder and carry out using CLAA expressions in CMOS logic. 
2. Designed 1 bit adder and carry out is tested by giving the single bit pulse patterns.
3. Extended this to 4 bit adder using CLAA expressions in CMOS logic. 194 transistors are required to implement a 4 bit CLAA logic cell. 
4. Designed 4 bit adder is verified by simulations. 
5. Subcircuit of 4 bit adder is created and saved as "new_CLAA_4bit.sub"
6. The 4-bit subcircuit is tested for different input bit patterns. 
7. Using the Subcircuit of 4 bit adder, 12 bit adder is constructed by connecting 3 subcircuits in cascade.
8. The 12 bit adder is tested for different pulse input patterns and the circuit is tested for the input pulse frequency of 250KHz.
9. The simulation results of S0 to S15 are getting as expected with Cout signal. 
10. The circuit is tested for the input pulse frequency of 200MHz and the output signal waveforms are having less than 0.5 as the peak peak output voltage. 
11. The supply voltage used is 1.3V in the simulations.
12. In the simulations, the width of the NMOS is considered as 10u and the PMOS width is 20u.
13. Simulations are carried out using SkyWater 130nm PDK Technology file in eSIM EDA tool.
14. I thank Mr. Kunal and his team for giving me the opportunity to participate in the Circuit Design and Simulation Marathon using eSim.  