Design of Exclusive-OR Gate using CMOS and SkyWater SKY130 PDK technology

This project is all about the design of Exclusive-OR gate also known as XOR gate,
whose output becomes logic high (i.e 1) only when the both the inputs are of opposite logic.
And becomes logic low (i.e. 0) if both of the inputs are of same logic.

Here is a brief descripton about the project.

>> At first by following the basic design of Exclusive OR gate using Static complementary CMOS design.
>> As you refer to the schematic diagram, the basic block of the XOR gate is designed by PMOS and NMOS.
>> After completing the design there comes a DC voltage source to biase all the MOSFETs.
>> This project was completely done using eSim and SkyWater 130nm technology.
>> The basic block was designed by using Eeschema of KiCad part of eSim tool.
>> Here two pulse sources were used for inputs.
>> After performing annotation, correction were performed post Electrical Rule Check.
>> Spice netlist was generated and later it was converted to Ngspice netlist by giving all the appropriate
values to the parameters like MOSFETs, Sources and transient time values.
>> Following Ngspice netlist, simulation was performed first for 180nm components provided by eSim tool.
>> And the Ngspice netlist was modified using SKY130 models and again it was simulated using Ngspice.
>> And here part of the project was completed.

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KiCad Spice Netlist
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* C:\Users\Home\eSim-Workspace\exor\exor.cir

* EESchema Netlist Version 1.1 (Spice format) creation date: 06/28/21 10:18:23

* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

* Sheet Name: /
U1  inputa plot_v1		
U2  inputb plot_v1		
U3  output plot_v1		
v1  inputa GND pulse		
v2  inputb GND pulse		
vd1  /vdd GND DC		
M10  Net-_M10-Pad1_ Net-_M1-Pad1_ GND GND mosfet_n		
M4  Net-_M2-Pad1_ inputa /vdd /vdd mosfet_p		
M3  Net-_M1-Pad1_ inputb /vdd /vdd mosfet_p		
M7  Net-_M7-Pad1_ Net-_M2-Pad1_ /vdd /vdd mosfet_p		
M11  Net-_M11-Pad1_ inputa /vdd /vdd mosfet_p		
M12  output Net-_M1-Pad1_ Net-_M11-Pad1_ /vdd mosfet_p		
M8  output inputb Net-_M7-Pad1_ /vdd mosfet_p		
M5  output inputa Net-_M5-Pad3_ GND mosfet_n		
M6  Net-_M5-Pad3_ inputb GND GND mosfet_n		
M9  output Net-_M2-Pad1_ Net-_M10-Pad1_ GND mosfet_n		
M1  Net-_M1-Pad1_ inputb GND GND mosfet_n		
M2  Net-_M2-Pad1_ inputa GND GND mosfet_n		

.end

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KiCad - Ngspice Netlist
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* c:\users\home\esim-workspace\exor\exor.cir

.include NMOS-180nm.lib
.include PMOS-180nm.lib
* u1  inputa plot_v1
* u2  inputb plot_v1
* u3  output plot_v1
v1  inputa gnd pulse(0 5 4m 0 0 10m 20m)
v2  inputb gnd pulse(0 5 2m 0 0 15m 30m)
vd1 /vdd gnd  dc 5
m10 net-_m10-pad1_ net-_m1-pad1_ gnd gnd CMOSN W=100u L=100u M=1
m4 net-_m2-pad1_ inputa /vdd /vdd CMOSP W=100u L=100u M=1
m3 net-_m1-pad1_ inputb /vdd /vdd CMOSP W=100u L=100u M=1
m7 net-_m7-pad1_ net-_m2-pad1_ /vdd /vdd CMOSP W=100u L=100u M=1
m11 net-_m11-pad1_ inputa /vdd /vdd CMOSP W=100u L=100u M=1
m12 output net-_m1-pad1_ net-_m11-pad1_ /vdd CMOSP W=100u L=100u M=1
m8 output inputb net-_m7-pad1_ /vdd CMOSP W=100u L=100u M=1
m5 output inputa net-_m5-pad3_ gnd CMOSN W=100u L=100u M=1
m6 net-_m5-pad3_ inputb gnd gnd CMOSN W=100u L=100u M=1
m9 output net-_m2-pad1_ net-_m10-pad1_ gnd CMOSN W=100u L=100u M=1
m1 net-_m1-pad1_ inputb gnd gnd CMOSN W=100u L=100u M=1
m2 net-_m2-pad1_ inputa gnd gnd CMOSN W=100u L=100u M=1
.tran 0.1e-03 100e-03 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
plot v(inputa)+12 v(inputb)+6 v(output)
.endc
.end
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