
 Design of CMOS Transmission Gate based 4:1 MUX using SKY130 PDK
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 Supriya Khatoniar, Tezpur University		email: supriyakhatoniar11@gmail.com		Date: 29/06/2021
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A MUX is a combinational circuit, also known as data selector that combines multiple inputs into a single data stream. 
The basic logic behind the transmission gate used in digital CMOS circuit design is to pass or block a signal from the input to the output. 
It consists of parallel connection of both p-channel and n-channel MOSFETs. A MUX using transmission gate results in reduction of area compared to conventional CMOS based MUX. 
The circuit has been designed using SKY130 technology. eSIM open source EDA tool is used to design, simulation and analyze the circuit.

Circuit Design, Generation of Netlist and Conversion of KiCad to Ngspice:
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 eSIM software is installed from its official website.
 After opening eSIM software and selecting the workspace path, a new project is created as 4_to_1_mux_txgate, 
  by making sure that file name as well as the path to the eSIM Workspace file does not contain any spaces in between.
 The project is opened in eSIM Schematic. By placing components (NMOS, PMOS, port, GND), 4 to 1 MUX is made, which is based on Transmission Gate Logic (or Pass Transistor).
  In this structure, 14 MOSFETs (7 NMOS +7 PMOS) are required. 
 For the control signals (S1, S1_bar, S2, S2_bar), two CMOS inverter are used.
 There are 4 ports for input to the MUX (input to the 4 Tranmission gate), 2 ports for Select lines (or control signals), one port for Vdd (power supply), and one for output port.
 The wire connections are done followed by labeling of ports, MOSFETs and other points as requied.
 After completing circuit design, electrical rule check is performed and then corrected schematic circuit is saved.
 Then Netlist (Spice Netlist) of the circuit is generated.
 In eSIM window, the circuit is converted from KiCad to Ngspice, for the simulation. Since there is no subcircuit in my circuit, so conversion is done by simply clicking on it.

Modifications of Spice Netlist with SKY130 components:
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 After successful of conversion from KiCad to Ngspice, SKY130 PDK is downloaded.
 A new folder is created in which sky130_fd_pr folder is added as well as .cir.out file of the circuit is pasted in .cir format.
 The .cir file of the circuit is then opened in Notepad.
 In Notepad file, library path of SKY130 is added.
 MOSFETs of eSIM designed circuit are replaced by SKY130 MOSFETs, with some specific width and length.
 Some modifications are done to make the code compatible with Ngspice and SKY130 PDK (e.g. placing of x, before MOSFET names, removing of /, etc.)
 Supply voltage of 3.3V and pulse voltage of 1.8V (amplitude)  is used for each input signals.
 pulse function is used to give the input signals with required amplitudes, pulse width and duration. No delay is used here.

Waveform Observation in Ngspice and W/L Modification:
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 In Notepad, plot function is used to plot the input and output waveforms. 
 The .cir file is run using Ngspice after doing each modification. It takes some time (6-7 minutes) to give the output which is basically of the linkage of SKY130 library files in it.
 To plot multiple signals in a single window, plot V(s1)+6 V(s2)+4 V(i0)+2  V(i1)  V(i2)-2 V(i3)-4 V(out)-6 is used, which is comfortable to compare the outputs with different input levels. 
  After successfully fixing the output waveforms with required modifications in length and width of MOSFETs the outputs are plotted separately (using plot function in separate line for each signals),
  so that actual voltage level is to be observed with respect to the input and output waveforms.
 To observe the significant variations of the output signal with the input signals, a small range (0 - 5ns) is considered. In this range, it is observed that the output is very sensitive to the change of input parameters.
  At first, for all NMOS, W= 0.42, L=0.5 and for all PMOS, W= 1, L=0.5 have given and carried out the simulation. Then, the MOSFETs which have much impact on the output signal are taken into consideration
  and to improve W/L ratio, width and length are modified from SKY130 library cells datasheets.
  By doing such modifications in some MOSFETs (namely, M5, M6, M8, M13, M14, M15, M16), a better output waveform is obtained with very small range of scale.
	(Modifications done for the mosfets-- M5, M13, M14, M16: W=.55, L=.15;  &  M6, M8, M16: W=1, L=.15)
 To see the effect of Width and Length, the values of all the W & L have been removed, and in this case the obtained output is undesirable.
 Now, W & L have been fixed in such combination in which I have obtained a better result in small nanosecond range (as mentioned above)
 While doing simulation in Ngspice, it is also observed when ther is multiple transitions at a single instant of time, it also effects on the output signal, i.e distortion.
  This phenomenon is observed in small nanosecond range (0 - 5ns).
 It is also observed that all the distortions which are obtained in small scale range are very negligible for a bit high scale, i.e. (0 - 50us). To design good circuit, it is better to check output variations in small range.
 In the final output, nanosecond range (0-50ns) is considered. A small spike obtained at the beginning is because of multiple transitions at the start node, which is not observable in microsecond range scale.
 All individual waveforms are merged into a single file.
(in the attached "4_to_1_mux_txgate.cir.out" file, both "plot" functions have written using comment statement, so that user can see the waveforms according to their wish)

Results:
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The resultant single output of Transmission Logic Gate based 4 to 1 MUX is obtained. It also verifies the truth table of 4 to 1 MUX. 
In my reference paper, authors have considered 45nm technology to design Transmission Logic Gate based 4 to1 MUX, and have obtained the rise and falltime of simulation is 100 fs of output during the power supply of 0.7.
