CIRCUIT:CMOS XOR GATE IN 130NM (XORGATE)
PROCEDURE:
1. DESIGNING THE CIRCUIT IN ESIM:
firstly i designed the reference in esim which included 6 mosfets (3-mosfet_p and 3-mosfet_n)
These mosfets are connected in the proper way as per the reference circuit.For mosfet_p M3 , the gate terminal is given the input (vin_a), vdd to the source(3)
and substrate(4). The output of M3 is given as input to the inverter stage.The vin_a is also given to the source(3) of mosfet_n(M2)and to the gate(2) of mosfet_n(M1)
The second input,vin_b is given to the source(3) of M1 and to the gate(2) of M2.The substrates of nMOS(M1 and M2) are grounded.The drain terminals(1) of M1 and M2 are 
connected to the drain (1) of nMOS M3 and then fed to the inverter comprising of mosfet_p M5 and mosfet_n M6.The output (vout) taken form the inverter is fed back to
the gate(2) of mosfet_p(M4).The source and substrate(3 and 4) of M4 and M5 are connected to Vdd and the  source and substrate  of M6 is grounded.
ALL voltages are given via ports and labelled properly. 
The schematic is saved and netlist generated.
2.MODIFYING THE NETLIST TO INCLUDE SKY130 PDK MODELS.
The .cir file in the XOR_GATE folder is is opened in notepad and the changes are made in the netlist.
The mosfets are replaced by the proper sky130 models(sky130_fd_pr__pfet_01v8 and sky130_fd_pr__nfet_01v8) as present in the library sky130.lib.spice in the models folder of sky130_fd_pr.
The w/l ratio is chosen as per the models(nfet_01v8 and pfet_01v8) form cells folder in sky130_fd_pr.
FOR nfet_01v8:M6,w=.42 l=.5 M2 AND M1, w=1 l=.5
FOR pfet_01v8;M5,w=1 l=.5 M4 w=.42 l=.5 M3,w=.42 l=.5
here w/l ratio of M2 >w/l ratio of M3 for XOR implementation.
vdd is given as 1.8v 
pulses are given as vin_a and vin_b with the follwing specifications: 
for vin_a the pulse amplitude is 1.8v the rise time is .4us , fall time is .4us pulse width is 7us and the time period of pulse as 20us.
for vin_b the pulse amplitude is 1.8v the rise time .4us , fall time .4us pulse width is 15us and time period 20us
the file is saved and and run ngspice. logically correct Waveforms are obtained.
3.ISSUES AND FIXES
for the inputs , when same pulses were given, the output was 0 (which though was logically correct as xor output is high only when the one input is high and other low)
SO, i chose the pulses with different pulse widths.( BUT with the same time period for uniform pulse width of the output)
At first i used the time period in nanoseconds there were very small voltage spikes of fractions of nanoseconds in the output but when the same analysis is done in 
microseconds , no such small spikes are obsereved .so i gave the pulse time in us.
besides earlier the fatal error occured but then i made sure that the sky130_fd_pr anf the circuit file are in the same folder to avid path clash.
Proper transient analysis and proper vdd was crucial, otherwise i obtained highly distorted waveform.
Its important the node volatges are properly named while giving plot command otherwise an error like " no such vector found" can occur .
