Hello Everyone,
This is readme file of a circuit design project submitted in the "Circuit Design and Simulation Marathon using eSim"
Conducted by FOSSEE, IIT Bombay, VLSI System Design Corp. Pvt. Ltd. and Ministry of Education, Govt. of India in June 2021.
In this Marathon I have designed a "Two Stage CMOS Operational Amplifier" with desired specifications using SKYWater 130nm PDK.
First stage is a Differential OpAmp and the second stage is the common source OpAmp.

The material submitted in the marathon is organized in the following ways:
1. Circuit Diagram  2. Result waveforms  3. NGSpice Netlist file with .cir.out extension   4. References

1. Circuit Diagram: I have attached the circuit diagram drawn in eSim with name "finalcktdig.png".
   I have also attached the pdf and image of hand drawn circuit diagram, in case if you couldn't understand the circuit diagram use it for better understanding, 
   with name "cktdig.pdf" and "ckt.jpg" 
   I have labled different nodes in my design just to make writing and reading of Spice Netlist easy.
   THERE ARE NO SUBCIRCUITS USED IN MY DESIGN. 

2. Resultant Waveforms and Discussion: I have attached the resultant waveform diagram with file name "finalwaveform.png".
   WORD OF CAUTION: The reference papers that I have used in my design have used Cadence Design Suit for designing circuit and waveform, 
   hence my resultant waveforms look different from the reference papers. I have used open source tool called NGSpice and eSim.
   PLEASE READ THIS SECTION CAREFULLY FOR BETTER UNDERSTANDING AND THEN TRY TO UNDERSTAND MY RESULTANT WAVEFORMS.
   BLUE LINE shows phase diagram of the ratio of Output Voltage to the Input Voltage in degrees i.e. (57.27273)*phase(V(vout)/(V(vin_p)-V(vin_n)))  in terms of NGSpice.
   As the reference papers said the propsed value of phase margin should be >= 60 degrees, on the carefull observation of resultant waveform we get the reqired phase margin correctly.
   My resultant wavforms have phase margin nearly equal to 60 degrees.  HENCE IT IS CORRECT.

   RED LINE shows gain of the ratio of Output Voltage to the Input Voltage in dB i.e. Value of (V(vout)/(V(vin_p)-V(vin_n))) in dB, in terms of NGSpice.
   However, the Y-axis has values in negative. Please ignore the negative sign and treat values as the positive values.
   Because, in the first stage differential opamp stage the gain Av1 is (theoritically) Av1 = -gm1*Zout1  , and 
   second stage is the common source OpAmp the gain is (theoritically) Av2 = 1/(sCc*Zout1), so the resultant gain of Two Stage CMOS Operational Amplifier is negative overall.
   So, while analyzing the resultant waveform, please ignore the negative sign in the result, and treat them as positive vales.
   As the reference papers said the propsed value of gain should be >= 60 dB, on the carefull observation of resultant waveform we get the reqired gain correctly.
   My resultant wavforms have gain nearly equal to 90 dB or 95 dB (which is still >60dB).   HENCE IT IS CORRECT.

3. NGSpice Netlist: I have attached the Spice Netlist with file name "cmosopamp.cir.out".
   I have used Skywater 130 nm PDK in my design, so for simulating my Spice netlist please make sure to have the Skywater 130nm models in the same directory as in the Spice netlist.
   Open Ubuntu Terminal, go to the directory where models and netlist is in, type: ngspice  cmosopamp.cir.out and then press enter and wait.

4. References: (i) M. I. Idris, N. Yusop, S. A. M. Chachuli, M.M. Ismail, Faiz Arith5 & A. M. Darsono. Low Power Operational Amplifier in 0.13um Technology.
                Published by Canadian Center of Science and Education, Modern Applied Science; Vol. 9, No. 1; 2015
                ResearchGate Link: https://www.researchgate.net/publication/283524419_Low_Power_Operational_Amplifier_in_013um_Technology

The Designer of the Circuit and the author of this README.txt file is ABHISHEK SINGH KUSHWAHA, Current Affiliation: Dept. of ECE, IIIT Dharwad, Karnataka, India.
He can be reached out at 19bec001@iiitdwd.ac.in OR abhishekiiitdwd@gmaildotcom

	
   