Vignesh Bharadwaj
BITS Pilani Hyderabad Campus
Low Power SRAM Cell

- CMOS INVERTER
The CMOS inverter comprises of one PMOS and one NMOS transistor.
I designed the CMOS inverter and then made it a subcircuit to use later in my actual design.

- CONVENTIONAL 6T SRAM
The 6T SRAM cell consists of two cross-coupled inverters to hold the data and two NMOS pass transistors to read or write data to the cell.
Initially while modeling the SRAM cell, I had tied up the substrate and the source terminals. This resulted in some errors in the waveforms.
After grounding the substrate terminals it worked perfectly.

- MTCMOS SRAM
I used the previously built 6T SRAM cell and added two sleep transistors between the SRAM cell and the power rails.
The sleep transistors are controlled by signals CLK and nCLK. To generate nCLK, the previously built CMOS inverter subcircuit was used with CLK as its input.
MTCMOS requires the sleep transistors to have a higher threshold voltage for lesser leakage.
The higher threshold voltage was abhieved by applying a substrate bias to both the sleep transistors.
Finally, the input pulses were given in an appropriate manner to obtain the output waveforms.