File: readme.txt
Title: Phase Frequency Detector for Phase Locked Loops


Overview:

The project aims to implement a phase-frequency detector which is often used as part of Phase Locked Loops or PLL in short. The circuit is implemented at the CMOS level using eSim EDA and SkyWater 130nm PDK technology.
Phase locked loops find their use case in many of the modern System on chip units to produce a square output with precise frequency and phase. Phase-frequency detector circuits are used to produce an error between present output to required output as an electrical signal. The scope of this project is limited to implementing a phase-frequency detector circuit though more functional units are required for a functional PLL.

Implementation:

The design requires two D type flip-flops and an AND gate. Since the D-flipflops were redundant and required a decent amount of logic, a sub-circuit was designed instead, and was included in the original design.
First the D flip flop was designed since it was crucial for the whole design. The flip flop required reset functionality which turned out to be pretty hard to have my head around and required a decent amount of investigation due to lack of technical knowledge. The AND gate, however was light in logical units and since the design required only one of it, the gate was designed raw in the actual circuit. A series NAND and a NOT gate were used to get the AND gate.
Finally, all the components were assembled as per the proposed circuit and tested to verify the desired output.
Each component was simulated with 3.3V as source voltage(Vcc) and 0V as ground reference.
3.3V was used as high reference and 0V as low for excitation of digital circuits.

The D-flipflop:
The D flip flop is used in digital circuits for temporary storage of date or as a delay element. The circuit has single input D. A clock is taken as reference. The data at D input is latched at the positive edge of the clock and is available as output at q.

Remarks:

During the process of implementation, eSim presented some new experience as well as difficulty compared to other circuit simulators like Multisim and falsted. The overall developing cycle was slow, especially at the testing part. Manual intervention to the spice file before its simulation was new and kind of painful since spice syntax was not familiar before. 
Though, intutive keyboard shortcuts were handy when some element is to be added to the design.

Overall, the whole process provided a great understanding of circuit design and implementation at industrial level.
Employing the SkyWater 130nm PDK technology, an Open source standard in our design was a boon to the knowledge of the overall circuit design from simulation to silicon level. The use of eSim as an open source circuit design tool in the whole process helped to understand it practically.
This program was helpful to get a hands on experience with industrial technology used in circuit design and synthesis.
