Project:- 3T DRAM Cell	          		
Creator:- Aastha Dave	           		
Institute:- Birla Institute of Technology and Science (BITS) Pilani, Hyderabad 
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Objective:- 
To design a 3T DRAM cell circuit on eSim based on Skywater130 technology node and carry out the circuit simulation on ngspice

Plan & Execution:-
The overall plan and execution of this project was as follows:
1. To design the 3T DRAM circuit provided in the reference paper chosen
2. To carry out electrical checks
3. To generate spice netlist and include sky130 library files for the MOSFETs followed by appropriate editing so as to name MOSFETs according to skywater naming convention and include transient analyses and voltage plots
4. To convert Kicad schematic to ngspice followed by ngspice simulation to obtain plots

Challenges faced:-
1. While the circuit design went about smoothly, running the .cir file in ngspice was the first challenge. Soon enough I recalled my experience with the linux environment and utilised the Windows command prompt to run ngspice as "ngspice file.cir" which solved my issue

2. The next challenge was to get past the warnings and errors that ngspice threw up. Most of my errors were resolved by reading up queries on sourceforge.net, however, one particular error which seemed to get in my way was - "mal fomed B line". Later, I changed the naming convention of voltage sources in my netlist to resolve the error. Later on I replaced all the ports with sources in my circuit so I would not have to separately define voltage sources in my netlist

3. I was intially working with pwl sources which gave rise to finite rise and fall times that interfered with the DRAM write and read logic. I played around with the PWL argument values so as to tackle this issue only to later give up and replace pwl with pulse sources

Input waveforms:-
The input voltages were given as follows:
vdd = 1.8V, DC
PC (pre-charge) = Square wave with period of 2ns
bit_write (Bit line write) = Pulse ON (1.8V) from 2-4ns (i.e. bit input = "11")
WR (Word line write) = Pulse ON (1.8V) for two durations, 2-3ns and 6-7ns
RD (Word line read) = Pulse ON (1.8V) for two durations, 4-5ns and 8-9ns

Output waveforms:-
vout (voltage at storage node) 
bit_read (Bit line read)

***Note: Firstly, in the reference paper waveforms, the voltage at storage node is a clear pulse signal that is ON from 2-6ns. In the simulation output, vout is fairly ON (with slight aberrations) between 2-6ns after which it dips to a negative voltage where it remains constant. This discrepancy could be due the fact that the authors of the paper have not included a storage capacitor at the storage node. The capacitor would ensure smooth discharge to GND at zero voltage. Secondly, the bit line read output is a pulse signal ON from 4-6ns. However, my simulation yields a bit_read that shoots up at 4ns, dips to zero and spikes at 6ns again before falling to zero, again with a few aberrations here and there. The reason for this discrepancy could be that in traditional DRAMS, the bit read output is sent to a sense amplifier circuitry which makes sense of the bits to discern the input that had initially been written into the DRAM cell. Since my circuit did not include sense amplifer ciruitry, a smooth ON pulse could not be obtained. However, the spikes at 4ns and 6ns could be discerned as a bit input of "11".










