#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_000001e759464bd0 .scope module, "tb_reconfig_transceiver" "tb_reconfig_transceiver" 2 8;
 .timescale -9 -12;
L_000001e7594ae090 .functor BUFZ 1, L_000001e759511270, C4<0>, C4<0>, C4<0>;
L_000001e759520088 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e75950fbc0_0 .net/2u *"_ivl_3", 0 0, L_000001e759520088;  1 drivers
o000001e7594baf18 .functor BUFZ 1, C4<z>; HiZ drive
; Elide local net with no drivers, v000001e759510480_0 name=_ivl_5
v000001e759510f20_0 .var "baud_div", 15 0;
v000001e75950f4e0_0 .net "busy", 0 0, L_000001e7594ae480;  1 drivers
v000001e75950f580_0 .var "clk", 0 0;
v000001e75950f800_0 .net "miso", 0 0, L_000001e7594ae090;  1 drivers
v000001e75950f9e0_0 .var "mode_sel", 1 0;
v000001e75950fa80_0 .net "mosi", 0 0, L_000001e759511270;  1 drivers
v000001e75950fc60_0 .var "rst_n", 0 0;
v000001e75950fd00_0 .net "rx_data", 7 0, L_000001e759512990;  1 drivers
v000001e7595123f0_0 .net "scl", 0 0, v000001e7594b23a0_0;  1 drivers
v000001e7595118b0_0 .net "sclk", 0 0, v000001e7594b1400_0;  1 drivers
L_000001e7594adfb0 .functor BUFT 1, C8<551>, C4<0>, C4<0>, C4<0>;
RS_000001e7594b9cb8 .resolv tri, L_000001e7594adfb0, L_000001e759511630, L_000001e759511c70;
v000001e7595116d0_0 .net8 "sda", 0 0, RS_000001e7594b9cb8;  3 drivers, strength-aware
v000001e759511590_0 .var "slave_ack_drive", 0 0;
v000001e759512710_0 .net "ss_n", 0 0, v000001e7594b1360_0;  1 drivers
v000001e759512350_0 .var "start", 0 0;
v000001e759512210_0 .var "tx_data", 7 0;
v000001e759511db0_0 .var "uart_rx", 0 0;
v000001e759512cb0_0 .net "uart_tx", 0 0, v000001e7594a7310_0;  1 drivers
v000001e759512a30_0 .net "xfer_done", 0 0, L_000001e759511a90;  1 drivers
E_000001e7594a0b10 .event anyedge, v000001e75950fb20_0;
E_000001e7594a0890 .event posedge, v000001e7594b1ae0_0;
E_000001e7594a0810 .event anyedge, v000001e7594b26c0_0, v000001e7594b14a0_0;
E_000001e7594a1c10 .event anyedge, v000001e7594a7310_0;
L_000001e759511630 .functor MUXZ 1, o000001e7594baf18, L_000001e759520088, v000001e759511590_0, C4<>;
S_000001e7594b5df0 .scope module, "dut" "reconfig_transceiver" 2 35, 3 4 0, S_000001e759464bd0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 2 "mode_sel";
    .port_info 3 /INPUT 1 "start";
    .port_info 4 /INPUT 16 "baud_div";
    .port_info 5 /INPUT 8 "tx_data";
    .port_info 6 /OUTPUT 8 "rx_data";
    .port_info 7 /OUTPUT 1 "busy";
    .port_info 8 /OUTPUT 1 "xfer_done";
    .port_info 9 /OUTPUT 1 "sclk";
    .port_info 10 /OUTPUT 1 "mosi";
    .port_info 11 /INPUT 1 "miso";
    .port_info 12 /OUTPUT 1 "ss_n";
    .port_info 13 /INOUT 1 "sda";
    .port_info 14 /OUTPUT 1 "scl";
    .port_info 15 /OUTPUT 1 "uart_tx";
    .port_info 16 /INPUT 1 "uart_rx";
L_000001e7594ae1e0 .functor AND 1, L_000001e759511130, v000001e759512350_0, C4<1>, C4<1>;
L_000001e7594ae020 .functor AND 1, L_000001e7595128f0, v000001e759512350_0, C4<1>, C4<1>;
L_000001e7594ade60 .functor AND 1, L_000001e759511d10, v000001e759512350_0, C4<1>, C4<1>;
L_000001e7594ae720 .functor NOT 1, L_000001e759511a90, C4<0>, C4<0>, C4<0>;
L_000001e7594ae480 .functor AND 1, v000001e759512350_0, L_000001e7594ae720, C4<1>, C4<1>;
L_000001e7595200d0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v000001e7594a6cd0_0 .net/2u *"_ivl_0", 1 0, L_000001e7595200d0;  1 drivers
L_000001e759520160 .functor BUFT 1, C4<10>, C4<0>, C4<0>, C4<0>;
v000001e75950f080_0 .net/2u *"_ivl_12", 1 0, L_000001e759520160;  1 drivers
v000001e75950fee0_0 .net *"_ivl_14", 0 0, L_000001e759511d10;  1 drivers
L_000001e7595201a8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v000001e759510020_0 .net/2u *"_ivl_18", 1 0, L_000001e7595201a8;  1 drivers
v000001e759510340_0 .net *"_ivl_2", 0 0, L_000001e759511130;  1 drivers
v000001e75950f300_0 .net *"_ivl_20", 0 0, L_000001e759511e50;  1 drivers
L_000001e7595201f0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v000001e7595108e0_0 .net/2u *"_ivl_22", 1 0, L_000001e7595201f0;  1 drivers
v000001e759510160_0 .net *"_ivl_24", 0 0, L_000001e759511950;  1 drivers
v000001e75950f440_0 .net *"_ivl_26", 0 0, L_000001e759511b30;  1 drivers
L_000001e759520238 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v000001e75950ff80_0 .net/2u *"_ivl_30", 1 0, L_000001e759520238;  1 drivers
v000001e7595103e0_0 .net *"_ivl_32", 0 0, L_000001e7595111d0;  1 drivers
L_000001e759520280 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v000001e75950f1c0_0 .net/2u *"_ivl_34", 1 0, L_000001e759520280;  1 drivers
v000001e75950f620_0 .net *"_ivl_36", 0 0, L_000001e759512c10;  1 drivers
v000001e7595107a0_0 .net *"_ivl_38", 7 0, L_000001e759511770;  1 drivers
v000001e759510de0_0 .net *"_ivl_42", 0 0, L_000001e7594ae720;  1 drivers
L_000001e759520118 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v000001e75950f120_0 .net/2u *"_ivl_6", 1 0, L_000001e759520118;  1 drivers
v000001e75950f3a0_0 .net *"_ivl_8", 0 0, L_000001e7595128f0;  1 drivers
v000001e759510520_0 .net "baud_div", 15 0, v000001e759510f20_0;  1 drivers
v000001e75950f6c0_0 .net "baud_tick", 0 0, v000001e7594b1b80_0;  1 drivers
v000001e759510840_0 .net "busy", 0 0, L_000001e7594ae480;  alias, 1 drivers
v000001e75950f8a0_0 .net "clk", 0 0, v000001e75950f580_0;  1 drivers
v000001e759510980_0 .net "i2c_done", 0 0, v000001e7594b2760_0;  1 drivers
v000001e759510660_0 .net "i2c_rx", 7 0, v000001e7594b19a0_0;  1 drivers
v000001e759510b60_0 .net "miso", 0 0, L_000001e7594ae090;  alias, 1 drivers
v000001e75950f940_0 .net "mode_sel", 1 0, v000001e75950f9e0_0;  1 drivers
v000001e75950fe40_0 .net "mosi", 0 0, L_000001e759511270;  alias, 1 drivers
v000001e75950f260_0 .net "rst_n", 0 0, v000001e75950fc60_0;  1 drivers
v000001e7595100c0_0 .net "rx_data", 7 0, L_000001e759512990;  alias, 1 drivers
v000001e759510ca0_0 .net "scl", 0 0, v000001e7594b23a0_0;  alias, 1 drivers
v000001e759510a20_0 .net "sclk", 0 0, v000001e7594b1400_0;  alias, 1 drivers
v000001e759510d40_0 .net8 "sda", 0 0, RS_000001e7594b9cb8;  alias, 3 drivers, strength-aware
v000001e759510e80_0 .net "spi_done", 0 0, v000001e7594b2b20_0;  1 drivers
v000001e7595102a0_0 .net "spi_rx", 7 0, v000001e7594b1a40_0;  1 drivers
v000001e759510700_0 .net "ss_n", 0 0, v000001e7594b1360_0;  alias, 1 drivers
v000001e759510ac0_0 .net "start", 0 0, v000001e759512350_0;  1 drivers
v000001e7595105c0_0 .net "tx_data", 7 0, v000001e759512210_0;  1 drivers
v000001e759510c00_0 .net "uart_done", 0 0, v000001e7594b1040_0;  1 drivers
v000001e759510200_0 .net "uart_rx", 0 0, v000001e759511db0_0;  1 drivers
v000001e75950fda0_0 .net "uart_rx_data", 7 0, v000001e7594b1900_0;  1 drivers
v000001e75950f760_0 .net "uart_tx", 0 0, v000001e7594a7310_0;  alias, 1 drivers
v000001e75950fb20_0 .net "xfer_done", 0 0, L_000001e759511a90;  alias, 1 drivers
L_000001e759511130 .cmp/eq 2, v000001e75950f9e0_0, L_000001e7595200d0;
L_000001e7595128f0 .cmp/eq 2, v000001e75950f9e0_0, L_000001e759520118;
L_000001e759511d10 .cmp/eq 2, v000001e75950f9e0_0, L_000001e759520160;
L_000001e759511e50 .cmp/eq 2, v000001e75950f9e0_0, L_000001e7595201a8;
L_000001e759511950 .cmp/eq 2, v000001e75950f9e0_0, L_000001e7595201f0;
L_000001e759511b30 .functor MUXZ 1, v000001e7594b1040_0, v000001e7594b2760_0, L_000001e759511950, C4<>;
L_000001e759511a90 .functor MUXZ 1, L_000001e759511b30, v000001e7594b2b20_0, L_000001e759511e50, C4<>;
L_000001e7595111d0 .cmp/eq 2, v000001e75950f9e0_0, L_000001e759520238;
L_000001e759512c10 .cmp/eq 2, v000001e75950f9e0_0, L_000001e759520280;
L_000001e759511770 .functor MUXZ 8, v000001e7594b1900_0, v000001e7594b19a0_0, L_000001e759512c10, C4<>;
L_000001e759512990 .functor MUXZ 8, L_000001e759511770, v000001e7594b1a40_0, L_000001e7595111d0, C4<>;
S_000001e7594af920 .scope module, "u_baud" "baud_gen" 3 30, 4 6 0, S_000001e7594b5df0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 16 "div";
    .port_info 3 /OUTPUT 1 "tick";
v000001e7594b1ae0_0 .net "clk", 0 0, v000001e75950f580_0;  alias, 1 drivers
v000001e7594b2120_0 .var "cnt", 15 0;
v000001e7594b2da0_0 .net "div", 15 0, v000001e759510f20_0;  alias, 1 drivers
v000001e7594b1f40_0 .net "rst_n", 0 0, v000001e75950fc60_0;  alias, 1 drivers
v000001e7594b1b80_0 .var "tick", 0 0;
E_000001e7594a1e10/0 .event negedge, v000001e7594b1f40_0;
E_000001e7594a1e10/1 .event posedge, v000001e7594b1ae0_0;
E_000001e7594a1e10 .event/or E_000001e7594a1e10/0, E_000001e7594a1e10/1;
S_000001e7594904a0 .scope module, "u_i2c" "i2c_master" 3 54, 5 5 0, S_000001e7594b5df0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "en";
    .port_info 3 /INPUT 1 "scl_tick";
    .port_info 4 /INPUT 8 "tx_data";
    .port_info 5 /OUTPUT 8 "rx_data";
    .port_info 6 /OUTPUT 1 "done";
    .port_info 7 /INOUT 1 "sda";
    .port_info 8 /OUTPUT 1 "scl";
P_000001e7594afab0 .param/l "ACK" 1 5 19, C4<011>;
P_000001e7594afae8 .param/l "DONE" 1 5 21, C4<101>;
P_000001e7594afb20 .param/l "IDLE" 1 5 16, C4<000>;
P_000001e7594afb58 .param/l "SHIFT" 1 5 18, C4<010>;
P_000001e7594afb90 .param/l "START" 1 5 17, C4<001>;
P_000001e7594afbc8 .param/l "STOP" 1 5 20, C4<100>;
o000001e7594b9b68 .functor BUFZ 1, C4<z>; HiZ drive
; Elide local net with no drivers, v000001e7594b1fe0_0 name=_ivl_0
v000001e7594b2c60_0 .var "ack_err", 0 0;
v000001e7594b2440_0 .var "bit_cnt", 3 0;
v000001e7594b1180_0 .net "clk", 0 0, v000001e75950f580_0;  alias, 1 drivers
v000001e7594b2760_0 .var "done", 0 0;
v000001e7594b2300_0 .net "en", 0 0, L_000001e7594ae020;  1 drivers
v000001e7594b12c0_0 .net "rst_n", 0 0, v000001e75950fc60_0;  alias, 1 drivers
v000001e7594b19a0_0 .var "rx_data", 7 0;
v000001e7594b23a0_0 .var "scl", 0 0;
v000001e7594b1220_0 .net "scl_tick", 0 0, v000001e7594b1b80_0;  alias, 1 drivers
v000001e7594b24e0_0 .net8 "sda", 0 0, RS_000001e7594b9cb8;  alias, 3 drivers, strength-aware
v000001e7594b14a0_0 .var "sda_oe", 0 0;
v000001e7594b2620_0 .var "sda_out", 0 0;
v000001e7594b2580_0 .var "shift", 7 0;
v000001e7594b26c0_0 .var "state", 2 0;
v000001e7594b1720_0 .net "tx_data", 7 0, v000001e759512210_0;  alias, 1 drivers
L_000001e759511c70 .functor MUXZ 1, o000001e7594b9b68, v000001e7594b2620_0, v000001e7594b14a0_0, C4<>;
S_000001e759490630 .scope module, "u_spi" "spi_master" 3 40, 6 4 0, S_000001e7594b5df0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "en";
    .port_info 3 /INPUT 1 "sclk_tick";
    .port_info 4 /INPUT 8 "tx_data";
    .port_info 5 /INPUT 1 "miso";
    .port_info 6 /OUTPUT 8 "rx_data";
    .port_info 7 /OUTPUT 1 "done";
    .port_info 8 /OUTPUT 1 "sclk";
    .port_info 9 /OUTPUT 1 "mosi";
    .port_info 10 /OUTPUT 1 "ss_n";
v000001e7594b1e00_0 .var "active", 0 0;
v000001e7594b2800_0 .var "bit_cnt", 3 0;
v000001e7594b1c20_0 .net "clk", 0 0, v000001e75950f580_0;  alias, 1 drivers
v000001e7594b2b20_0 .var "done", 0 0;
v000001e7594b2940_0 .net "en", 0 0, L_000001e7594ae1e0;  1 drivers
v000001e7594b28a0_0 .net "miso", 0 0, L_000001e7594ae090;  alias, 1 drivers
v000001e7594b2e40_0 .net "mosi", 0 0, L_000001e759511270;  alias, 1 drivers
v000001e7594b29e0_0 .net "rst_n", 0 0, v000001e75950fc60_0;  alias, 1 drivers
v000001e7594b1a40_0 .var "rx_data", 7 0;
v000001e7594b1400_0 .var "sclk", 0 0;
v000001e7594b2a80_0 .net "sclk_tick", 0 0, v000001e7594b1b80_0;  alias, 1 drivers
v000001e7594b1ea0_0 .var "shift_rx", 7 0;
v000001e7594b1cc0_0 .var "shift_tx", 7 0;
v000001e7594b1360_0 .var "ss_n", 0 0;
v000001e7594b10e0_0 .net "tx_data", 7 0, v000001e759512210_0;  alias, 1 drivers
L_000001e759511270 .part v000001e7594b1cc0_0, 7, 1;
S_000001e7594849f0 .scope module, "u_uart" "uart_core" 3 66, 7 6 0, S_000001e7594b5df0;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "en";
    .port_info 3 /INPUT 1 "baud_tick";
    .port_info 4 /INPUT 8 "tx_data";
    .port_info 5 /OUTPUT 8 "rx_data";
    .port_info 6 /OUTPUT 1 "done";
    .port_info 7 /OUTPUT 1 "tx";
    .port_info 8 /INPUT 1 "rx";
P_000001e7594907c0 .param/l "RDATA" 1 7 22, C4<01>;
P_000001e7594907f8 .param/l "RIDLE" 1 7 22, C4<00>;
P_000001e759490830 .param/l "RSTOP" 1 7 22, C4<10>;
P_000001e759490868 .param/l "TDATA" 1 7 17, C4<01>;
P_000001e7594908a0 .param/l "TIDLE" 1 7 17, C4<00>;
P_000001e7594908d8 .param/l "TSTOP" 1 7 17, C4<10>;
v000001e7594b2bc0_0 .net "baud_tick", 0 0, v000001e7594b1b80_0;  alias, 1 drivers
v000001e7594b0fa0_0 .net "clk", 0 0, v000001e75950f580_0;  alias, 1 drivers
v000001e7594b1040_0 .var "done", 0 0;
v000001e7594b1d60_0 .net "en", 0 0, L_000001e7594ade60;  1 drivers
v000001e7594b1540_0 .var "rbit", 2 0;
v000001e7594b15e0_0 .var "rshift", 7 0;
v000001e7594b1680_0 .net "rst_n", 0 0, v000001e75950fc60_0;  alias, 1 drivers
v000001e7594b17c0_0 .var "rstate", 1 0;
v000001e7594b1860_0 .net "rx", 0 0, v000001e759511db0_0;  alias, 1 drivers
v000001e7594b1900_0 .var "rx_data", 7 0;
v000001e7594a7090_0 .var "rx_done", 0 0;
v000001e7594a7630_0 .var "tbit", 2 0;
v000001e7594a7130_0 .var "tshift", 7 0;
v000001e7594a6f50_0 .var "tstate", 1 0;
v000001e7594a7310_0 .var "tx", 0 0;
v000001e7594a6a50_0 .net "tx_data", 7 0, v000001e759512210_0;  alias, 1 drivers
    .scope S_000001e7594af920;
T_0 ;
    %wait E_000001e7594a1e10;
    %load/vec4 v000001e7594b1f40_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_0.0, 8;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001e7594b2120_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b1b80_0, 0;
    %jmp T_0.1;
T_0.0 ;
    %load/vec4 v000001e7594b2120_0;
    %load/vec4 v000001e7594b2da0_0;
    %cmp/e;
    %jmp/0xz  T_0.2, 4;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001e7594b2120_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b1b80_0, 0;
    %jmp T_0.3;
T_0.2 ;
    %load/vec4 v000001e7594b2120_0;
    %addi 1, 0, 16;
    %assign/vec4 v000001e7594b2120_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b1b80_0, 0;
T_0.3 ;
T_0.1 ;
    %jmp T_0;
    .thread T_0;
    .scope S_000001e759490630;
T_1 ;
    %wait E_000001e7594a1e10;
    %load/vec4 v000001e7594b29e0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b1e00_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b1360_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b1400_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000001e7594b2800_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b2b20_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001e7594b1a40_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001e7594b1cc0_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001e7594b1ea0_0, 0;
    %jmp T_1.1;
T_1.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b2b20_0, 0;
    %load/vec4 v000001e7594b2940_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_1.4, 9;
    %load/vec4 v000001e7594b1e00_0;
    %nor/r;
    %and;
T_1.4;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.2, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b1e00_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b1360_0, 0;
    %load/vec4 v000001e7594b10e0_0;
    %assign/vec4 v000001e7594b1cc0_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000001e7594b2800_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b1400_0, 0;
    %jmp T_1.3;
T_1.2 ;
    %load/vec4 v000001e7594b1e00_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_1.7, 9;
    %load/vec4 v000001e7594b2a80_0;
    %and;
T_1.7;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.5, 8;
    %load/vec4 v000001e7594b1400_0;
    %inv;
    %assign/vec4 v000001e7594b1400_0, 0;
    %load/vec4 v000001e7594b1400_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.8, 8;
    %load/vec4 v000001e7594b1ea0_0;
    %parti/s 7, 0, 2;
    %load/vec4 v000001e7594b28a0_0;
    %concat/vec4; draw_concat_vec4
    %assign/vec4 v000001e7594b1ea0_0, 0;
    %load/vec4 v000001e7594b1cc0_0;
    %parti/s 7, 0, 2;
    %concati/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b1cc0_0, 0;
    %load/vec4 v000001e7594b2800_0;
    %addi 1, 0, 4;
    %assign/vec4 v000001e7594b2800_0, 0;
    %load/vec4 v000001e7594b2800_0;
    %cmpi/e 7, 0, 4;
    %jmp/0xz  T_1.10, 4;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b1e00_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b1360_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b2b20_0, 0;
    %load/vec4 v000001e7594b1ea0_0;
    %parti/s 7, 0, 2;
    %load/vec4 v000001e7594b28a0_0;
    %concat/vec4; draw_concat_vec4
    %assign/vec4 v000001e7594b1a40_0, 0;
T_1.10 ;
T_1.8 ;
T_1.5 ;
T_1.3 ;
T_1.1 ;
    %jmp T_1;
    .thread T_1;
    .scope S_000001e7594904a0;
T_2 ;
    %wait E_000001e7594a1e10;
    %load/vec4 v000001e7594b12c0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.0, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v000001e7594b26c0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b23a0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b14a0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b2620_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000001e7594b2440_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b2760_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001e7594b19a0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b2c60_0, 0;
    %jmp T_2.1;
T_2.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b2760_0, 0;
    %load/vec4 v000001e7594b26c0_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 3;
    %cmp/u;
    %jmp/1 T_2.2, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 3;
    %cmp/u;
    %jmp/1 T_2.3, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 3;
    %cmp/u;
    %jmp/1 T_2.4, 6;
    %dup/vec4;
    %pushi/vec4 3, 0, 3;
    %cmp/u;
    %jmp/1 T_2.5, 6;
    %dup/vec4;
    %pushi/vec4 4, 0, 3;
    %cmp/u;
    %jmp/1 T_2.6, 6;
    %dup/vec4;
    %pushi/vec4 5, 0, 3;
    %cmp/u;
    %jmp/1 T_2.7, 6;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v000001e7594b26c0_0, 0;
    %jmp T_2.9;
T_2.2 ;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b23a0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b14a0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b2620_0, 0;
    %load/vec4 v000001e7594b2300_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.10, 8;
    %load/vec4 v000001e7594b1720_0;
    %assign/vec4 v000001e7594b2580_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000001e7594b2440_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b2620_0, 0;
    %pushi/vec4 1, 0, 3;
    %assign/vec4 v000001e7594b26c0_0, 0;
T_2.10 ;
    %jmp T_2.9;
T_2.3 ;
    %load/vec4 v000001e7594b1220_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.12, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b23a0_0, 0;
    %pushi/vec4 2, 0, 3;
    %assign/vec4 v000001e7594b26c0_0, 0;
T_2.12 ;
    %jmp T_2.9;
T_2.4 ;
    %load/vec4 v000001e7594b1220_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.14, 8;
    %load/vec4 v000001e7594b23a0_0;
    %inv;
    %assign/vec4 v000001e7594b23a0_0, 0;
    %load/vec4 v000001e7594b23a0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.16, 8;
    %load/vec4 v000001e7594b2580_0;
    %parti/s 1, 7, 4;
    %assign/vec4 v000001e7594b2620_0, 0;
    %load/vec4 v000001e7594b2580_0;
    %parti/s 7, 0, 2;
    %concati/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b2580_0, 0;
    %jmp T_2.17;
T_2.16 ;
    %load/vec4 v000001e7594b2440_0;
    %addi 1, 0, 4;
    %assign/vec4 v000001e7594b2440_0, 0;
    %load/vec4 v000001e7594b2440_0;
    %cmpi/e 7, 0, 4;
    %jmp/0xz  T_2.18, 4;
    %pushi/vec4 3, 0, 3;
    %assign/vec4 v000001e7594b26c0_0, 0;
T_2.18 ;
T_2.17 ;
T_2.14 ;
    %jmp T_2.9;
T_2.5 ;
    %load/vec4 v000001e7594b1220_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.20, 8;
    %load/vec4 v000001e7594b23a0_0;
    %inv;
    %assign/vec4 v000001e7594b23a0_0, 0;
    %load/vec4 v000001e7594b23a0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.22, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b14a0_0, 0;
    %jmp T_2.23;
T_2.22 ;
    %load/vec4 v000001e7594b24e0_0;
    %assign/vec4 v000001e7594b2c60_0, 0;
    %load/vec4 v000001e7594b1720_0;
    %assign/vec4 v000001e7594b19a0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b14a0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b2620_0, 0;
    %pushi/vec4 4, 0, 3;
    %assign/vec4 v000001e7594b26c0_0, 0;
T_2.23 ;
T_2.20 ;
    %jmp T_2.9;
T_2.6 ;
    %load/vec4 v000001e7594b1220_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.24, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b23a0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b2620_0, 0;
    %pushi/vec4 5, 0, 3;
    %assign/vec4 v000001e7594b26c0_0, 0;
T_2.24 ;
    %jmp T_2.9;
T_2.7 ;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594b2760_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v000001e7594b26c0_0, 0;
    %jmp T_2.9;
T_2.9 ;
    %pop/vec4 1;
T_2.1 ;
    %jmp T_2;
    .thread T_2;
    .scope S_000001e7594849f0;
T_3 ;
    %wait E_000001e7594a1e10;
    %load/vec4 v000001e7594b1680_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.0, 8;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001e7594a6f50_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594a7310_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v000001e7594a7630_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001e7594a7130_0, 0;
    %jmp T_3.1;
T_3.0 ;
    %load/vec4 v000001e7594a6f50_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 2;
    %cmp/u;
    %jmp/1 T_3.2, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 2;
    %cmp/u;
    %jmp/1 T_3.3, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 2;
    %cmp/u;
    %jmp/1 T_3.4, 6;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001e7594a6f50_0, 0;
    %jmp T_3.6;
T_3.2 ;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594a7310_0, 0;
    %load/vec4 v000001e7594b1d60_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.7, 8;
    %load/vec4 v000001e7594a6a50_0;
    %assign/vec4 v000001e7594a7130_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594a7310_0, 0;
    %pushi/vec4 1, 0, 2;
    %assign/vec4 v000001e7594a6f50_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v000001e7594a7630_0, 0;
T_3.7 ;
    %jmp T_3.6;
T_3.3 ;
    %load/vec4 v000001e7594b2bc0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.9, 8;
    %load/vec4 v000001e7594a7130_0;
    %parti/s 1, 0, 2;
    %assign/vec4 v000001e7594a7310_0, 0;
    %load/vec4 v000001e7594a7130_0;
    %ix/load 4, 1, 0;
    %flag_set/imm 4, 0;
    %shiftr 4;
    %assign/vec4 v000001e7594a7130_0, 0;
    %load/vec4 v000001e7594a7630_0;
    %addi 1, 0, 3;
    %assign/vec4 v000001e7594a7630_0, 0;
    %load/vec4 v000001e7594a7630_0;
    %cmpi/e 7, 0, 3;
    %jmp/0xz  T_3.11, 4;
    %pushi/vec4 2, 0, 2;
    %assign/vec4 v000001e7594a6f50_0, 0;
T_3.11 ;
T_3.9 ;
    %jmp T_3.6;
T_3.4 ;
    %load/vec4 v000001e7594b2bc0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.13, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594a7310_0, 0;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001e7594a6f50_0, 0;
T_3.13 ;
    %jmp T_3.6;
T_3.6 ;
    %pop/vec4 1;
T_3.1 ;
    %jmp T_3;
    .thread T_3;
    .scope S_000001e7594849f0;
T_4 ;
    %wait E_000001e7594a1e10;
    %load/vec4 v000001e7594b1680_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.0, 8;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001e7594b17c0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v000001e7594b1540_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001e7594b15e0_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001e7594b1900_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594a7090_0, 0;
    %jmp T_4.1;
T_4.0 ;
    %load/vec4 v000001e7594b2bc0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.2, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594a7090_0, 0;
    %load/vec4 v000001e7594b17c0_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 2;
    %cmp/u;
    %jmp/1 T_4.4, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 2;
    %cmp/u;
    %jmp/1 T_4.5, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 2;
    %cmp/u;
    %jmp/1 T_4.6, 6;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001e7594b17c0_0, 0;
    %jmp T_4.8;
T_4.4 ;
    %load/vec4 v000001e7594b1860_0;
    %cmpi/e 0, 0, 1;
    %jmp/0xz  T_4.9, 4;
    %pushi/vec4 1, 0, 2;
    %assign/vec4 v000001e7594b17c0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v000001e7594b1540_0, 0;
T_4.9 ;
    %jmp T_4.8;
T_4.5 ;
    %load/vec4 v000001e7594b1860_0;
    %load/vec4 v000001e7594b15e0_0;
    %parti/s 7, 1, 2;
    %concat/vec4; draw_concat_vec4
    %assign/vec4 v000001e7594b15e0_0, 0;
    %load/vec4 v000001e7594b1540_0;
    %addi 1, 0, 3;
    %assign/vec4 v000001e7594b1540_0, 0;
    %load/vec4 v000001e7594b1540_0;
    %cmpi/e 7, 0, 3;
    %jmp/0xz  T_4.11, 4;
    %pushi/vec4 2, 0, 2;
    %assign/vec4 v000001e7594b17c0_0, 0;
T_4.11 ;
    %jmp T_4.8;
T_4.6 ;
    %load/vec4 v000001e7594b15e0_0;
    %assign/vec4 v000001e7594b1900_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001e7594a7090_0, 0;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001e7594b17c0_0, 0;
    %jmp T_4.8;
T_4.8 ;
    %pop/vec4 1;
T_4.2 ;
T_4.1 ;
    %jmp T_4;
    .thread T_4;
    .scope S_000001e7594849f0;
T_5 ;
    %wait E_000001e7594a1e10;
    %load/vec4 v000001e7594b1680_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_5.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001e7594b1040_0, 0;
    %jmp T_5.1;
T_5.0 ;
    %load/vec4 v000001e7594a7090_0;
    %assign/vec4 v000001e7594b1040_0, 0;
T_5.1 ;
    %jmp T_5;
    .thread T_5;
    .scope S_000001e759464bd0;
T_6 ;
    %wait E_000001e7594a1c10;
    %load/vec4 v000001e759512cb0_0;
    %store/vec4 v000001e759511db0_0, 0, 1;
    %jmp T_6;
    .thread T_6, $push;
    .scope S_000001e759464bd0;
T_7 ;
    %wait E_000001e7594a0810;
    %load/vec4 v000001e7594b26c0_0;
    %cmpi/e 3, 0, 3;
    %flag_get/vec4 4;
    %jmp/0 T_7.2, 4;
    %load/vec4 v000001e7594b14a0_0;
    %pushi/vec4 0, 0, 1;
    %cmp/e;
    %flag_get/vec4 4;
    %and;
T_7.2;
    %flag_set/vec4 8;
    %jmp/0xz  T_7.0, 8;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001e759511590_0, 0, 1;
    %jmp T_7.1;
T_7.0 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001e759511590_0, 0, 1;
T_7.1 ;
    %jmp T_7;
    .thread T_7, $push;
    .scope S_000001e759464bd0;
T_8 ;
    %delay 5000, 0;
    %load/vec4 v000001e75950f580_0;
    %inv;
    %store/vec4 v000001e75950f580_0, 0, 1;
    %jmp T_8;
    .thread T_8;
    .scope S_000001e759464bd0;
T_9 ;
    %vpi_call 2 69 "$dumpfile", "reconfig_transceiver.vcd" {0 0 0};
    %vpi_call 2 70 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001e759464bd0 {0 0 0};
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001e75950f580_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001e75950fc60_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001e759512350_0, 0, 1;
    %pushi/vec4 0, 0, 2;
    %store/vec4 v000001e75950f9e0_0, 0, 2;
    %pushi/vec4 4, 0, 16;
    %store/vec4 v000001e759510f20_0, 0, 16;
    %pushi/vec4 0, 0, 8;
    %store/vec4 v000001e759512210_0, 0, 8;
    %delay 20000, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001e75950fc60_0, 0, 1;
    %pushi/vec4 0, 0, 2;
    %store/vec4 v000001e75950f9e0_0, 0, 2;
    %pushi/vec4 165, 0, 8;
    %store/vec4 v000001e759512210_0, 0, 8;
    %wait E_000001e7594a0890;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001e759512350_0, 0, 1;
    %wait E_000001e7594a0890;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001e759512350_0, 0, 1;
T_9.0 ;
    %load/vec4 v000001e759512a30_0;
    %cmpi/ne 1, 0, 1;
    %jmp/0xz T_9.1, 6;
    %wait E_000001e7594a0b10;
    %jmp T_9.0;
T_9.1 ;
    %load/vec4 v000001e75950fd00_0;
    %cmpi/ne 165, 0, 8;
    %jmp/0xz  T_9.2, 6;
    %vpi_call 2 85 "$display", "FAIL: SPI loopback mismatch, got %h", v000001e75950fd00_0 {0 0 0};
    %jmp T_9.3;
T_9.2 ;
    %vpi_call 2 87 "$display", "PASS: SPI loopback OK (%h)", v000001e75950fd00_0 {0 0 0};
T_9.3 ;
    %delay 50000, 0;
    %pushi/vec4 1, 0, 2;
    %store/vec4 v000001e75950f9e0_0, 0, 2;
    %pushi/vec4 60, 0, 8;
    %store/vec4 v000001e759512210_0, 0, 8;
    %wait E_000001e7594a0890;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001e759512350_0, 0, 1;
    %wait E_000001e7594a0890;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001e759512350_0, 0, 1;
T_9.4 ;
    %load/vec4 v000001e759512a30_0;
    %cmpi/ne 1, 0, 1;
    %jmp/0xz T_9.5, 6;
    %wait E_000001e7594a0b10;
    %jmp T_9.4;
T_9.5 ;
    %load/vec4 v000001e75950fd00_0;
    %cmpi/ne 60, 0, 8;
    %jmp/0xz  T_9.6, 6;
    %vpi_call 2 95 "$display", "FAIL: I2C self-check mismatch, got %h", v000001e75950fd00_0 {0 0 0};
    %jmp T_9.7;
T_9.6 ;
    %vpi_call 2 97 "$display", "PASS: I2C transfer acknowledged (%h)", v000001e75950fd00_0 {0 0 0};
T_9.7 ;
    %delay 50000, 0;
    %pushi/vec4 2, 0, 2;
    %store/vec4 v000001e75950f9e0_0, 0, 2;
    %pushi/vec4 85, 0, 8;
    %store/vec4 v000001e759512210_0, 0, 8;
    %wait E_000001e7594a0890;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001e759512350_0, 0, 1;
    %wait E_000001e7594a0890;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001e759512350_0, 0, 1;
T_9.8 ;
    %load/vec4 v000001e759512a30_0;
    %cmpi/ne 1, 0, 1;
    %jmp/0xz T_9.9, 6;
    %wait E_000001e7594a0b10;
    %jmp T_9.8;
T_9.9 ;
    %load/vec4 v000001e75950fd00_0;
    %cmpi/ne 85, 0, 8;
    %jmp/0xz  T_9.10, 6;
    %vpi_call 2 105 "$display", "FAIL: UART loopback mismatch, got %h", v000001e75950fd00_0 {0 0 0};
    %jmp T_9.11;
T_9.10 ;
    %vpi_call 2 107 "$display", "PASS: UART loopback OK (%h)", v000001e75950fd00_0 {0 0 0};
T_9.11 ;
    %delay 50000, 0;
    %vpi_call 2 110 "$display", "ALL TESTS COMPLETE" {0 0 0};
    %vpi_call 2 111 "$finish" {0 0 0};
    %end;
    .thread T_9;
# The file index is used to find the file name in the following table.
:file_names 8;
    "N/A";
    "<interactive>";
    "tb_reconfig_transceiver.v";
    "reconfig_transceiver .v";
    "baud_gen.v";
    "i2c_master.v";
    "spi_master.v";
    "uart_core.v";
