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eSim NGVERI SIMULATION INSTRUCTIONS & README
Project: Circuit-Level Modelling And Verification Of A Manchester Transceiver
Author: Akshat Sharma
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please read this carefully before running the project.

*** IMPORTANT OS COMPATIBILITY NOTE ***
This mixed-signal project utilizes custom Verilog digital logic blocks to bypass complex sequential archiving constraints and ensure simulator stability. Because this project uses eSim's NgVeri feature, it compiles Verilog into OS-specific machine binaries (.cm files). 

To ensure the simulation runs flawlessly on your specific operating system (Linux, Windows, or macOS), you MUST generate the local code models on your machine before running the simulation. 

Please follow these exact steps:

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PHASE 1: GENERATE THE ENCODER MODEL
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1. Open eSim and load this project folder.
2. Do NOT click 'Simulate' yet.
3. On the left eSim toolbar, click the "NgVeri" tool icon.
4. Click "Browse" and select the provided "manchester_enc.v" file located inside this project folder.
5. Click "Generate" (or select the option to convert code to Ngspice).
6. When the terminal prompts you for the Top Level Module name, type exactly: manchester_enc
7. Press Enter and wait for the "Process Completed Successfully" message.
8. Repeat for "manchester_dec.v" file too.

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PHASE 2: GENERATE THE DECODER MODEL
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8. In the same NgVeri window, click "Browse" again and select the provided "manchester_dec.v" file.
9. Click "Generate".
10. When prompted for the Top Level Module name, type exactly: manchester_dec
11. Press Enter and wait for the "Process Completed Successfully" message.
12. You may now close the NgVeri window. Both custom chips are now natively compiled for your system.

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PHASE 3: CONVERT AND SIMULATE
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13. From the main eSim window, click "KiCad to Ngspice Converter".
14. Navigate to the 'Transient Analysis' tab and verify the following values:
    - Step Time: 10u
    - Stop Time: 10m
15. Click "Convert" and wait for the success message.
16. Finally, click the "Simulate" button on the main eSim toolbar.

--- PLOTTING THE RESULTS ---
When the eSim Plotting GUI opens, please select the following traces to verify the transceiver's operation:
- v(original_data): The baseband digital input.
- v(encoded_tx): The Manchester encoded signal traversing the channel.
- v(decoded_tx): The perfectly recovered data at the receiver.

For internal timing verification, you may also plot v(v_pulse2_) and v(v_pulse3_) to observe the 0.75ms sampling clock phase delay.

Thank you for your time in exploring this design!